Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11663391 | Latch-up avoidance for sea-of-gates | David Wolpert, Ryan Michael Kruse, Leon Sigal, Richard Edward Serton, Matthew S. Angyal +1 more | 2023-05-30 |
| 10103083 | Integrated circuits with Peltier cooling provided by back-end wiring | Siyuranga O. Koswatta, Sungjae Lee, Lan Luo, Scott K. Springer | 2018-10-16 |
| 9773717 | Integrated circuits with peltier cooling provided by back-end wiring | Siyuranga O. Koswatta, Sungjae Lee, Lan Luo, Scott K. Springer | 2017-09-26 |
| 9484246 | Buried signal transmission line | Anthony I. Chou, Arvind Kumar, Sungjae Lee | 2016-11-01 |
| 9240406 | Precision trench capacitor | Kai D. Feng, Dan Moy, Chengwen Pei, Robert R. Robison, Pinping Sun +1 more | 2016-01-19 |
| 8809187 | Body contacts for FET in SOI SRAM array | Yue Tan, Zhibin Ren, Haining Yang | 2014-08-19 |
| 8338292 | Body contacts for FET in SOI SRAM array | Yue Tan, Zhibin Ren, Haining Yang | 2012-12-25 |
| 8020138 | Voltage island performance/leakage screen monitor for IP characterization | Bruce Balch, Nazmul Habib, Susan K. Lichtensteiger, Daniel Stasiak | 2011-09-13 |
| 7989922 | Highly tunable metal-on-semiconductor trench varactor | Randy W. Mann, Jae-Eun Park | 2011-08-02 |
| 7470613 | Dual damascene multi-level metallization | Birendra Agarwala, Eric M. Coker, Anthony Correale, Jr., Hazara S. Rathore, Timothy D. Sullivan | 2008-12-30 |
| 7260810 | Method of extracting properties of back end of line (BEOL) chip architecture | Ronald G. Filippi, Giovanni Fiorenza, Xiao Hu Liu, Conal E. Murray, Gregory A. Northrop +2 more | 2007-08-21 |
| 7224063 | Dual-damascene metallization interconnection | Birendra Agarwala, Eric M. Coker, Anthony Correale, Jr., Hazara S. Rathore, Timothy D. Sullivan | 2007-05-29 |
| 7217978 | SRAM memories and microprocessors having logic portions implemented in high-performance silicon substrates and SRAM array portions having field effect transistors with linked bodies and method for making same | Rajiv V. Joshi, Yue Tan, Kerry Bernstein | 2007-05-15 |
| 6531759 | Alpha particle shield for integrated circuit | Henry A. Nye, III, Charles R. Davis, Theodore H. Zabel, Phillip J. Restle | 2003-03-11 |
| 6518670 | Electrically porous on-chip decoupling/shielding layer | Jack A. Mandelman, Ronald G. Filippi, Jeffrey P. Gambino | 2003-02-11 |
| 6417572 | Process for producing metal interconnections and product produced thereby | Dureseti Chidambarrao, Ronald G. Filippi, Robert Rosenberg, Thomas M. Shaw, Timothy D. Sullivan | 2002-07-09 |
| 6258710 | Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity | Hazara S. Rathore, Hormazdyar M. Dalal, Paul S. McLaughlin, Du Nguyen, Richard G. Smith +1 more | 2001-07-10 |
| 6202191 | Electromigration resistant power distribution network | Ronald G. Filippi, Phillip Lin, Thomas M. Shaw | 2001-03-13 |
| 6069051 | Method of producing planar metal-to-metal capacitor for use in integrated circuits | Du Nguyen, Hazara S. Rathore, George S. Prokop, Craig R. Gruszecki | 2000-05-30 |
| 6069068 | Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity | Hazara S. Rathore, Hormazdyar M. Dalal, Paul S. McLaughlin, Du Nguyen, Richard G. Smith +1 more | 2000-05-30 |