Issued Patents All Time
Showing 26–50 of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11581315 | Self-aligned gate edge trigate and finFET devices | Biswajeet Guha, Tahir Ghani, Christopher KENYON, Leonard P. GULER | 2023-02-14 |
| 11563081 | Self-aligned gate edge and local interconnect | Milton Clair Webb, Mark Bohr, Tahir Ghani | 2023-01-24 |
| 11532724 | Selective gate spacers for semiconductor devices | Scott B. Clendenning, Florian Gstrein, Rami Hourani, Patricio E. Romero, Grant Kloster +1 more | 2022-12-20 |
| 11456357 | Self-aligned gate edge architecture with alternate channel material | Biswajeet Guha, Anupama Bowonder, William Hsu, Mehmet O. Baykan, Tahir Ghani | 2022-09-27 |
| 11329138 | Self-aligned gate endcap (SAGE) architecture having endcap plugs | Sairam Subramanian, Christopher KENYON, Sridhar Govindaraju, Chia-Hong Jan, Mark Liu +1 more | 2022-05-10 |
| 11282930 | Contact architecture for capacitance reduction and satisfactory contact resistance | Rishabh Mehandru, Pratik A. Patel, Thomas T. TROEGER | 2022-03-22 |
| 11264453 | Methods of doping fin structures of non-planar transistor devices | Cory E. Weber, Aaron D. Lilak, Aaron A. Budrevich | 2022-03-01 |
| 11222947 | Methods of doping fin structures of non-planar transistor devices | Cory E. Weber, Aaron D. Lilak, Aaron A. Budrevich | 2022-01-11 |
| 11217582 | Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls | Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Chia-Hong Jan, Nick Lindert +2 more | 2022-01-04 |
| 11205708 | Dual self-aligned gate endcap (SAGE) architectures | Sairam Subramanian, Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Chia-Hong Jan +2 more | 2021-12-21 |
| 11183592 | Field effect transistor with a hybrid gate spacer including a low-k dielectric material | Pratik A. Patel | 2021-11-23 |
| 11152461 | Semiconductor layer between source/drain regions and gate spacers | Rishabh Mehandru, Anupama Bowonder, Biswajeet Guha, Tahir Ghani, Stephen M. Cea +2 more | 2021-10-19 |
| 11127841 | Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions | Michael L. Hattendorf, Tahir Ghani | 2021-09-21 |
| 11101268 | Transistors employing non-selective deposition of source/drain material | Karthik Jambunathan, Scott Maddox, Ritesh Jhaveri, Pratik A. Patel, Anand S. Murthy +1 more | 2021-08-24 |
| 11094831 | Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device | Rishabh Mehandru, Stephen M. Cea | 2021-08-17 |
| 11056492 | Dense memory arrays utilizing access transistors with back-side contacts | Wilfred Gomes, Mauro J. Kobrinsky, Elliot N. Tan, Tahir Ghani, Swaminathan Sivakumar +1 more | 2021-07-06 |
| 11043492 | Self-aligned gate edge trigate and finFET devices | Biswajeet Guha, Tahir Ghani, Christopher KENYON, Leonard P. GULER | 2021-06-22 |
| 11011620 | Techniques for increasing channel region tensile strain in n-MOS devices | Rishabh Mehandru, Cory E. Weber, Anand S. Murthy, Karthik Jambunathan, Glenn A. Glass +2 more | 2021-05-18 |
| 10998423 | Fabrication of multi-channel nanowire devices with self-aligned internal spacers and SOI FinFETs using selective silicon nitride capping | Van H. Le, Scott B. Clendenning, Martin M. Mitan | 2021-05-04 |
| 10971600 | Selective gate spacers for semiconductor devices | Scott B. Clendenning, Florian Gstrein, Rami Hourani, Patricio E. Romero, Grant Kloster +1 more | 2021-04-06 |
| 10896963 | Semiconductor device contacts with increased contact area | Rishabh Mehandru, Tahir Ghani | 2021-01-19 |
| 10872960 | Contact architecture for capacitance reduction and satisfactory contact resistance | Rishabh Mehandru, Pratik A. Patel, Thomas T. TROEGER | 2020-12-22 |
| 10790354 | Self-aligned gate edge and local interconnect | Milton Clair Webb, Mark Bohr, Tahir Ghani | 2020-09-29 |
| 10770458 | Nanowire transistor device architectures | Rishabh Mehandru, Tahir Ghani, Seiyon Kim | 2020-09-08 |
| 10756215 | Selective deposition utilizing sacrificial blocking layers for semiconductor devices | Grant Kloster, Scott B. Clendenning, Rami Hourani, Patricio E. Romero, Florian Gstrein | 2020-08-25 |