Issued Patents All Time
Showing 51–75 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11600696 | Sub-fin leakage reduction for template strained materials | Stephen M. Cea, Anupama Bowonder, Juhyung Nam, Willy Rachmady | 2023-03-07 |
| 11573798 | Stacked transistors with different gate lengths in different device strata | Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Ehren Mannebach, Cheng-Ying Huang +2 more | 2023-02-07 |
| 11557676 | Device, method and system to provide a stressed channel of a transistor | Stephen M. Cea, Tahir Ghani, Anand S. Murthy | 2023-01-17 |
| 11552104 | Stacked transistors with dielectric between channels of different device strata | Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Ehren Mannebach, Cheng-Ying Huang +3 more | 2023-01-10 |
| 11538806 | Gate-all-around integrated circuit structures having high mobility | Roza Kotlyar, Stephen M. Cea, Biswajeet Guha, Dax M. Crum, Tahir Ghani | 2022-12-27 |
| 11527640 | Wrap-around contact structures for semiconductor nanowires and nanoribbons | Tahir Ghani, Stephen M. Cea, Biswajeet Guha | 2022-12-13 |
| 11527613 | Removal of a bottom-most nanowire from a nanowire device stack | Aaron D. Lilak, Patrick H. Keys, Sean T. Ma, Stephen M. Cea | 2022-12-13 |
| 11527612 | Gate-all-around integrated circuit structures having vertically discrete source or drain structures | Glenn A. Glass, Anand S. Murthy, Biswajeet Guha, Dax M. Crum, Sean T. Ma +3 more | 2022-12-13 |
| 11522072 | Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices | Patrick Morrow, Ranjith Kumar, Cory E. Weber, Seiyon Kim, Stephen M. Cea +1 more | 2022-12-06 |
| 11515420 | Contacts to n-type transistors with X-valley layer over L-valley channels | Dax M. Crum, Cory E. Weber, Harold W. Kennel, Benjamin Chu-Kung | 2022-11-29 |
| 11482621 | Vertically stacked CMOS with upfront M0 interconnect | Willy Rachmady, Patrick Morrow, Aaron D. Lilak, Cheng-Ying Huang, Gilbert Dewey +4 more | 2022-10-25 |
| 11462536 | Integrated circuit structures having asymmetric source and drain structures | Anupama Bowonder, Mark Bohr, Tahir Ghani | 2022-10-04 |
| 11456372 | Multi-height finfet device by selective oxidation | Seiyon Kim, Gopinath Bhimarasetti, Rafael Rios, Jack T. Kavalieros, Tahir Ghani +1 more | 2022-09-27 |
| 11430868 | Buried etch-stop layer to help control transistor source/drain depth | Biswajeet Guha, Anupama Bowonder, Anand S. Murthy, Tahir Ghani, Stephen M. Cea | 2022-08-30 |
| 11411119 | Double gated thin film transistors | Aaron D. Lilak, Van H. Le, Abhishek A. Sharma, Tahir Ghani, Gilbert Dewey +1 more | 2022-08-09 |
| 11404319 | Vertically stacked finFETs and shared gate patterning | Aaron D. Lilak, Sean T. Ma, Justin R. Weber, Stephen M. Cea, Patrick Morrow +1 more | 2022-08-02 |
| 11398479 | Heterogeneous Ge/III-V CMOS transistor structures | Willy Rachmady, Abhishek A. Sharma, Ravi Pillarisetty, Patrick Morrow, Aaron D. Lilak +2 more | 2022-07-26 |
| 11393722 | Isolation wall stressor structures to improve channel stress and their methods of fabrication | Aaron D. Lilak, Christopher J. Jezewski, Willy Rachmady, Gilbert Dewey, Anh Phan | 2022-07-19 |
| 11393818 | Stacked transistors with Si PMOS and high mobility thin film transistor NMOS | Gilbert Dewey, Ravi Pillarisetty, Abhishek A. Sharma, Aaron D. Lilak, Willy Rachmady +5 more | 2022-07-19 |
| 11387238 | Non-silicon N-Type and P-Type stacked transistors for integrated circuit devices | Gilbert Dewey, Patrick Morrow, Ravi Pillarisetty, Cheng-Ying Huang, Willy Rachmady +1 more | 2022-07-12 |
| 11374004 | Pedestal fin structure for stacked transistor integration | Aaron D. Lilak, Anh Phan, Gilbert Dewey, Willy Rachmady, Stephen M. Cea +5 more | 2022-06-28 |
| 11373999 | Deep trench via for three-dimensional integrated circuit | Yih Wang, Mauro J. Kobrinsky, Tahir Ghani, Mark Bohr, Marni Nabors | 2022-06-28 |
| 11374024 | Integrated circuits with stacked transistors and methods of manufacturing the same using processes which fabricate lower gate structures following completion of portions of an upper transistor | Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Anh Phan | 2022-06-28 |
| 11374100 | Source or drain structures with contact etch stop layer | Cory Bomberger, Anupama Bowonder, Biswajeet Guha, Anand S. Murthy, Tahir Ghani | 2022-06-28 |
| 11367722 | Stacked nanowire transistor structure with different channel geometries for stress | Aaron D. Lilak, Stephen M. Cea, Gilbert Dewey, Willy Rachmady, Roza Kotlyar +4 more | 2022-06-21 |