Issued Patents All Time
Showing 76–100 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11362189 | Stacked self-aligned transistors with single workfunction metal | Aaron D. Lilak, Willy Rachmady, Gilbert Dewey, Justin R. Weber | 2022-06-14 |
| 11342432 | Gate-all-around integrated circuit structures having insulator fin on insulator substrate | Aaron D. Lilak, Cory E. Weber, Willy Rachmady, Varun MISHRA | 2022-05-24 |
| 11335807 | Isolation schemes for gate-all-around transistor devices | Stephen M. Cea, Biswajeet Guha, Tahir Ghani, William Hsu | 2022-05-17 |
| 11328951 | Transistor cells including a deep via lined wit h a dielectric material | Patrick Morrow, Mauro J. Kobrinsky | 2022-05-10 |
| 11282930 | Contact architecture for capacitance reduction and satisfactory contact resistance | Pratik A. Patel, Thomas T. TROEGER, Szuya S. Liao | 2022-03-22 |
| 11282861 | Dynamic logic built with stacked transistors sharing a common gate | Donald W. Nelson | 2022-03-22 |
| 11276780 | Transistor contact area enhancement | Tahir Ghani, Stephen M. Cea | 2022-03-15 |
| 11264405 | Semiconductor diodes employing back-side semiconductor or metal | Patrick Morrow, Nathan Jack | 2022-03-01 |
| 11264512 | Thin film transistors having U-shaped features | Gilbert Dewey, Aaron D. Lilak, Van H. Le, Abhishek A. Sharma, Tahir Ghani +6 more | 2022-03-01 |
| 11264501 | Device, method and system for promoting channel stress in a NMOS transistor | Anand S. Murthy, Karthik Jambunathan, Cory Bomberger | 2022-03-01 |
| 11264500 | Device isolation | Stephen M. Cea, Tahir Ghani | 2022-03-01 |
| 11257929 | Stacked transistors | Patrick Morrow, Aaron D. Lilak | 2022-02-22 |
| 11239236 | Forksheet transistor architectures | Aaron D. Lilak, Ehren Mannebach, Patrick Morrow, Willy Rachmady | 2022-02-01 |
| 11239232 | Isolation walls for vertically stacked transistor structures | Aaron D. Lilak, Patrick Morrow, Gilbert Dewey, Willy Rachmady | 2022-02-01 |
| 11227799 | Wrap-around contact structures for semiconductor fins | — | 2022-01-18 |
| 11201221 | Backside contact structures and fabrication for metal on both sides of devices | Patrick Morrow, Aaron D. Lilak, Kimin Jun | 2021-12-14 |
| 11152461 | Semiconductor layer between source/drain regions and gate spacers | Anupama Bowonder, Biswajeet Guha, Tahir Ghani, Stephen M. Cea, William Hsu +2 more | 2021-10-19 |
| 11152396 | Semiconductor device having stacked transistors and multiple threshold voltage control | Aaron D. Lilak, Gilbert Dewey, Willy Rachmady | 2021-10-19 |
| 11139241 | Integrated circuit device with crenellated metal trace layout | Patrick Morrow, Mauro J. Kobrinsky, Mark Bohr, Tahir Ghani, Ranjith Kumar | 2021-10-05 |
| 11107811 | Metallization structures under a semiconductor device layer | Aaron D. Lilak, Patrick Morrow, Stephen M. Cea | 2021-08-31 |
| 11107924 | Systems and methods to reduce FinFET gate capacitance | Aaron D. Lilak, Patrick Morrow | 2021-08-31 |
| 11094716 | Source contact and channel interface to reduce body charging from band-to-band tunneling | Dipanjan Basu, Seung Hoon Sung | 2021-08-17 |
| 11094831 | Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device | Szuya S. Liao, Stephen M. Cea | 2021-08-17 |
| 11075119 | Vertically stacked transistors in a pin | Aaron D. Lilak, Sean T. Ma, Justin R. Weber, Patrick Morrow | 2021-07-27 |
| 11075198 | Stacked transistor architecture having diverse fin geometry | Aaron D. Lilak, Cheng-Ying Huang, Gilbert Dewey, Willy Rachmady | 2021-07-27 |