Issued Patents All Time
Showing 101–125 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11075202 | Bottom fin trim isolation aligned with top gate for stacked device architectures | Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Patrick Morrow | 2021-07-27 |
| 11049861 | Method, device and system to provide capacitance for a dynamic random access memory cell | Aaron D. Lilak, Patrick Morrow, Donald W. Nelson, Stephen M. Cea | 2021-06-29 |
| 11011620 | Techniques for increasing channel region tensile strain in n-MOS devices | Cory E. Weber, Anand S. Murthy, Karthik Jambunathan, Glenn A. Glass, Jiong Zhang +2 more | 2021-05-18 |
| 11011537 | Vertical interconnect methods for stacked device architectures using direct self assembly with high operational parallelization and improved scalability | Aaron D. Lilak, Patrick Theofanis, Patrick Morrow, Stephen M. Cea | 2021-05-18 |
| 10991696 | Vertically stacked devices with self-aligned regions formed by direct self assembly (DSA) processing | Aaron D. Lilak, Patrick Theofanis, Cory E. Weber, Stephen M. Cea | 2021-04-27 |
| 10978590 | Methods and apparatus to remove epitaxial defects in semiconductors | Aaron D. Lilak, Patrick Morrow, Patrick H. Keys | 2021-04-13 |
| 10937665 | Methods and apparatus for gettering impurities in semiconductors | Aaron D. Lilak, Harold W. Kennel, Patrick Morrow, Stephen M. Cea | 2021-03-02 |
| 10910405 | Backside fin recess control with multi-HSI option | Aaron D. Lilak, Patrick Morrow, Stephen M. Cea, Cory E. Weber | 2021-02-02 |
| 10896907 | Retrograde transistor doping by heterojunction materials | Patrick H. Keys, Hei Kam, Aaron A. Budrevich | 2021-01-19 |
| 10896963 | Semiconductor device contacts with increased contact area | Tahir Ghani, Szuya S. Liao | 2021-01-19 |
| 10892326 | Removal of a bottom-most nanowire from a nanowire device stack | Aaron D. Lilak, Patrick H. Keys, Sean T. Ma, Stephen M. Cea | 2021-01-12 |
| 10886217 | Integrated circuit device with back-side interconnection to deep source/drain semiconductor | Patrick Morrow, Mauro J. Kobrinsky, Mark Bohr, Tahir Ghani | 2021-01-05 |
| 10886272 | Techniques for forming dual-strain fins for co-integrated n-MOS and p-MOS devices | Stephen M. Cea, Anupama Bowonder, Anand S. Murthy, Tahir Ghani | 2021-01-05 |
| 10872820 | Integrated circuit structures | Bruce A. Block, Valluri Rao, Patrick Morrow, Doug B. Ingerly, Kimin Jun +3 more | 2020-12-22 |
| 10872960 | Contact architecture for capacitance reduction and satisfactory contact resistance | Pratik A. Patel, Thomas T. TROEGER, Szuya S. Liao | 2020-12-22 |
| 10861870 | Inverted staircase contact for density improvement to 3D stacked devices | Aaron D. Lilak, Patrick Morrow | 2020-12-08 |
| 10847635 | Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices | Patrick Morrow, Ranjith Kumar, Cory E. Weber, Seiyon Kim, Stephen M. Cea +1 more | 2020-11-24 |
| 10790281 | Stacked channel structures for MOSFETs | Roza Kotlyar, Stephen M. Cea, Patrick H. Keys | 2020-09-29 |
| 10784358 | Backside contact structures and fabrication for metal on both sides of devices | Patrick Morrow, Aaron D. Lilak, Kimin Jun | 2020-09-22 |
| 10770458 | Nanowire transistor device architectures | Tahir Ghani, Szuya S. Liao, Seiyon Kim | 2020-09-08 |
| 10636907 | Deep EPI enabled by backside reveal for stress enhancement and contact | Aaron D. Lilak, Stephen M. Cea, Patrick Morrow, Patrick H. Keys | 2020-04-28 |
| 10600810 | Backside fin recess control with multi-hsi option | Aaron D. Lilak, Patrick Morrow, Stephen M. Cea, Cory E. Weber | 2020-03-24 |
| 10573715 | Backside isolation for integrated circuit | Aaron D. Lilak, Harold W. Kennel, Paul B. Fischer, Stephen M. Cea | 2020-02-25 |
| 10546873 | Integrated circuit with stacked transistor devices | Aaron D. Lilak | 2020-01-28 |
| 10529827 | Long channel MOS transistors for low leakage applications on a short channel CMOS chip | Patrick Morrow, Paul B. Fischer, Aaron D. Lilak, Stephen M. Cea | 2020-01-07 |