Issued Patents All Time
Showing 126–131 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10497781 | Methods for doping a sub-fin region of a semiconductor structure by backside reveal and associated devices | Aaron D. Lilak, Stephen M. Cea, Cory E. Weber | 2019-12-03 |
| 10468489 | Isolation structures for an integrated circuit element and method of making same | Aaron D. Lilak, Uygar E. Avci, David L. Kencke, Patrick Morrow, Kerryann Marrietta Foley +1 more | 2019-11-05 |
| 10453967 | Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device | Szuya S. Liao, Stephen M. Cea | 2019-10-22 |
| 10411090 | Hybrid trigate and nanowire CMOS device architecture | Cory E. Weber, Stephen M. Cea | 2019-09-10 |
| 10304946 | Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices | Patrick Morrow, Ranjith Kumar, Cory E. Weber, Seiyon Kim, Stephen M. Cea +1 more | 2019-05-28 |
| 7943992 | Metal gate structures with recessed channel | Bernhard Sell | 2011-05-17 |