Issued Patents All Time
Showing 126–150 of 213 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8664057 | High-K metal gate electrode structures formed by early cap layer adaptation | Rohit Pal, Sven Beyer, Richard J. Carter | 2014-03-04 |
| 8658509 | Semiconductor resistors formed at a lower height level in a semiconductor device comprising metal gates | Ralf Richter, Jens Heinrich | 2014-02-25 |
| 8652913 | Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss | Andreas Gehring, Maciej Wiatr, Thorsten Kammler, Roman Boschke, Casey Scott | 2014-02-18 |
| 8652889 | Fin-transistor formed on a patterned STI region by late fin etch | Peter Baars, Richard J. Carter, Frank Ludwig | 2014-02-18 |
| 8647952 | Encapsulation of closely spaced gate electrode structures | Peter Baars, Richard J. Carter | 2014-02-11 |
| 8614123 | Method of forming a semiconductor device by using sacrificial gate electrodes and sacrificial self-aligned contact structures | Peter Baars, Erik Geiss | 2013-12-24 |
| 8609510 | Replacement metal gate diffusion break formation | Srinvasa Banna | 2013-12-17 |
| 8609485 | Methods of forming efuse devices | Andreas Kurz, Christoph Schwan | 2013-12-17 |
| 8603893 | Methods for fabricating FinFET integrated circuits on bulk semiconductor substrates | Francis C. Tambwe, Frank Scott Johnson | 2013-12-10 |
| 8580643 | Threshold voltage adjustment in a Fin transistor by corner implantation | Tim Baldauf, Tom Herrmann, Stefan Flachowsky, Ralf Illgen | 2013-11-12 |
| 8557666 | Methods for fabricating integrated circuits | Peter Baars, Erik Geiss | 2013-10-15 |
| 8530894 | Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions | Anthony Mowry, Casey Scott, Vassilios Papageorgiou, Markus Lenski, Andreas Gehring | 2013-09-10 |
| 8497554 | Semiconductor device comprising metal gate structures formed by a replacement gate approach and efuses including a silicide | Jens Heinrich, Ralf Richter | 2013-07-30 |
| 8450163 | Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approach | Sven Beyer, Klaus Hempel, Roland Stejskal, Thilo Scheiper, Andreas Kurz +2 more | 2013-05-28 |
| 8440516 | Method of forming a field effect transistor | Thorsten Kammler, Jan Hoentschel, Manfred Horstmann | 2013-05-14 |
| 8404550 | Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement | Thilo Scheiper, Sven Beyer, Jan Hoentschel | 2013-03-26 |
| 8390127 | Contact trenches for enhancing stress transfer in closely spaced transistors | Jan Hoentschel, Heike Salz | 2013-03-05 |
| 8377761 | SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device | Andreas Gehring, Jan Hoentschel | 2013-02-19 |
| 8357978 | Methods of forming semiconductor devices with replacement gate structures | Peter Baars, Richard J. Carter | 2013-01-22 |
| 8349695 | Work function adjustment in high-k gate stacks including gate dielectrics of different thickness | Thilo Scheiper, Martin Trentzsch | 2013-01-08 |
| 8349694 | Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy | Stephan Kronholz, Markus Lenski, Martin Gerhardt | 2013-01-08 |
| 8338306 | Forming semiconductor resistors in a semiconductor device comprising metal gates by increasing etch resistivity of the resistors | Jens Heinrich, Ralf Richter, Katja Steffen, Johannes Groschopf, Frank Seliger +2 more | 2012-12-25 |
| 8334569 | Transistor with embedded Si/Ge material having enhanced across-substrate uniformity | Robert Neil Mulfinger, Jan Hoentschel, Casey Scott | 2012-12-18 |
| 8298885 | Semiconductor device comprising metal gates and a silicon containing resistor formed on an isolation structure | Andrew Waite | 2012-10-30 |
| 8298924 | Method for differential spacer removal by wet chemical etch process and device with differential spacer structure | Maciej Wiatr, Frank Wirbeleit, Andreas Gehring | 2012-10-30 |