Issued Patents All Time
Showing 176–200 of 213 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7790537 | Method for creating tensile strain by repeatedly applied stress memorization techniques | Anthony Mowry, Andreas Gehring, Maciej Wiatr | 2010-09-07 |
| 7772077 | Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region | Andreas Gehring, Anthony Mowry, Manuj Rathor | 2010-08-10 |
| 7767540 | Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility | Igor Peidous, Thorsten Kammler | 2010-08-03 |
| 7763515 | Transistor with embedded silicon/germanium material on a strained semiconductor on insulator substrate | Thorsten Kammler, Roman Boschke, Manfred Horstmann | 2010-07-27 |
| 7723195 | Method of forming a field effect transistor | Thorsten Kammler, Jan Hoentschel, Manfred Horstmann | 2010-05-25 |
| 7723174 | CMOS device comprising MOS transistors with recessed drain and source areas and a SI/GE material in the drain and source areas of the PMOS transistor | Andrew Waite, Gunter Grasshoff | 2010-05-25 |
| 7719060 | Tensile strain source using silicon/germanium in globally strained silicon | Karla Romero, Manfred Horstmann | 2010-05-18 |
| 7713763 | Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions | Anthony Mowry, Casey Scott, Vassilios Papageorgiou, Markus Lenski, Andreas Gehring | 2010-05-11 |
| 7696052 | Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions | Thorsten Kammler, Jan Hoentschel, Manfred Horstmann, Peter Javorka, Joe Bloomquist | 2010-04-13 |
| 7659213 | Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same | Thorsten Kammler, Jan Hoentschel, Manfred Horstmann | 2010-02-09 |
| 7586153 | Technique for forming recessed strained drain/source regions in NMOS and PMOS transistors | Jan Hoentschel, Thorsten Kammler, Michael Raab | 2009-09-08 |
| 7579262 | Different embedded strain layers in PMOS and NMOS transistors and a method of forming the same | Jan Hoentschel, Manfred Horstmann, Thorsten Kammler | 2009-08-25 |
| 7569437 | Formation of transistor having a strained channel region including a performance enhancing material composition utilizing a mask pattern | Frank Wirbeleit, Roman Boschke | 2009-08-04 |
| 7544999 | SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate | Derick J. Wristers, Mark B. Fuselier | 2009-06-09 |
| 7510926 | Technique for providing stress sources in MOS transistors in close proximity to a channel region | Thorsten Kammler, Jan Hoentschel, Manfred Horstmann | 2009-03-31 |
| 7432136 | Transistors with controllable threshold voltages, and various methods of making and operating same | Mark B. Fuselier, Derick J. Wristers | 2008-10-07 |
| 7402497 | Transistor device having an increased threshold stability without drive current degradation | Thorsten Kammler, Jan Hoentschel, Manfred Horstmann | 2008-07-22 |
| 7399663 | Embedded strain layer in thin SOI transistors and a method of forming the same | Jan Hoentschel, Manfred Horstmann, Thorsten Kammler | 2008-07-15 |
| 7381622 | Method for forming embedded strained drain/source regions based on a combined spacer and cavity etch process | Andreas Hellmich, Gunter Grasshoff, Fernando Luiz Koch, Thorsten Kammler | 2008-06-03 |
| 7381624 | Technique for forming a substrate having crystalline semiconductor regions of different characteristics located above a crystalline bulk substrate | Thorsten Kammler, Michael Raab, Manfred Horstmann | 2008-06-03 |
| 7354836 | Technique for forming a strained transistor by a late amorphization and disposable spacers | Jan Hoentschel, Gert Burbach, Peter Javorka | 2008-04-08 |
| 7354839 | Gate structure and a transistor having asymmetric spacer elements and methods of forming the same | Gert Burbach, David C. Greenlaw | 2008-04-08 |
| 7354838 | Technique for forming a contact insulation layer with enhanced stress transfer efficiency | Thorsten Kammler, Markus Lenski | 2008-04-08 |
| 7344984 | Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors | Jan Hoentschel, Markus Lenski, Peter Javorka | 2008-03-18 |
| 7335568 | Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same | Derick J. Wristers, Mark B. Fuselier | 2008-02-26 |