AW

Andy Wei

Globalfoundries: 132 patents #8 of 4,424Top 1%
AM AMD: 61 patents #89 of 9,279Top 1%
IN Intel: 20 patents #2,022 of 30,777Top 7%
📍 Yamhill, OR: #1 of 29 inventorsTop 4%
🗺 Oregon: #50 of 28,073 inventorsTop 1%
Overall (All Time): #2,893 of 4,157,543Top 1%
213
Patents All Time

Issued Patents All Time

Showing 201–213 of 213 patents

Patent #TitleCo-InventorsDate
7329571 Technique for providing multiple stress sources in NMOS and PMOS transistors Jan Hoentschel, Manfred Horstmann, Thorsten Kammler 2008-02-12
7316975 Method of forming sidewall spacers Markus Lenski, Wolfgang Buchholtz, Michael Raab 2008-01-08
7180136 Biased, triple-well fully depleted SOI structure Derick J. Wristers, Mark B. Fuselier 2007-02-20
7138320 Advanced technique for forming a transistor having raised drain and source regions Ralf van Bentum, Scott Luning 2006-11-21
7129142 Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same Derick J. Wristers, Mark B. Fuselier 2006-10-31
6919236 Biased, triple-well fully depleted SOI structure, and various methods of making and operating same Derick J. Wristers, Mark B. Fuselier 2005-07-19
6884702 Method of making an SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate Derick J. Wristers, Mark B. Fuselier 2005-04-26
6876037 Fully-depleted SOI device Derick J. Wristers, Mark B. Fuselier 2005-04-05
6864516 SOI MOSFET junction degradation using multiple buried amorphous layers Akif Sultan, David Wu 2005-03-08
6780686 Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions Derick J. Wristers, Mark B. Fuselier 2004-08-24
6737332 Semiconductor device formed over a multiple thickness buried oxide layer, and methods of making same Mark B. Fuselier, Derick J. Wristers 2004-05-18
6583016 Doped spacer liner for improved transistor performance Mark B. Fuselier, Ping-Chin Yeh 2003-06-24
6506654 Source-side stacking fault body-tie for partially-depleted SOI MOSFET hysteresis control Witold P. Maszara, Mario M. Pelella 2003-01-14