Issued Patents All Time
Showing 26–50 of 227 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12051632 | Semiconductor package structure and method for forming semiconductor package structure | Wei-Hung Lin, Ming-Da Cheng, Mirng-Ji Lii | 2024-07-30 |
| 12051622 | Passivation layer and planarization layer and method of forming the same | Ming-Da Cheng, Tzy-Kuang Lee, Hao-Chun Liu, Chih-Hsien Lin, Ching-Wen Hsiao | 2024-07-30 |
| 12046548 | Chip package with redistribution structure having multiple chips | Shin-Puu Jeng, Po-Yao Chuang, Feng-Cheng Hsu, Shuo-Mao Chen, Techi Wong | 2024-07-23 |
| 12021045 | Semiconductor device and method of manufacture | Po-Yao Chuang, Ming-Chih Yew, Shin-Puu Jeng | 2024-06-25 |
| 11996606 | Heterogeneous antenna in fan-out package | Po-Yao Chuang, Shin-Puu Jeng | 2024-05-28 |
| 11996372 | Semiconductor device and method of manufacture | Po-Yao Chuang, Shin-Puu Jeng | 2024-05-28 |
| 11967579 | Method for forming package structure with cavity substrate | Ming-Da Cheng, Mirng-Ji Lii | 2024-04-23 |
| 11961762 | Package component with stepped passivation layer | Ming-Da Cheng, Tzy-Kuang Lee, Song-Bor Lee, Wen-Hsiung Lu, Wen-Che Chang | 2024-04-16 |
| 11955423 | Semiconductor device and method | Ting-Li Yang, Ming-Da Cheng, Yung-Han Chuang, Hsueh-Sheng Wang | 2024-04-09 |
| 11948892 | Formation method of chip package with fan-out feature | Meng-Liang Lin, Po-Yao Chuang, Techi Wong, Shin-Puu Jeng | 2024-04-02 |
| 11935866 | Semiconductor device having reduced bump height variation | Jing-Cheng Lin | 2024-03-19 |
| 11908790 | Chip structure with conductive via structure and method for forming the same | Ting-Li Yang, Ching-Wen Hsiao, Hong-Seng Shue, Yu-Tse Su | 2024-02-20 |
| 11901302 | InFO-POP structures with TIVs having cavities | Jing-Cheng Lin, Chen-Hua Yu | 2024-02-13 |
| 11862588 | Semiconductor device and method | Chen-Shien Chen, Ting-Li Yang, Chien-Chen Li, Ming-Da Cheng | 2024-01-02 |
| 11855047 | Chip package structure with conductive shielding film | Chen-Hua Yu, An-Jhih Su, Jing-Cheng Lin | 2023-12-26 |
| 11855059 | Fan-out package with cavity substrate | Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin | 2023-12-26 |
| 11854964 | Structure and formation method of semiconductor device with conductive bumps | Ming-Da Cheng, Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Yung-Sheng Lin | 2023-12-26 |
| 11854998 | Semiconductor device and method of manufacture | Jing-Cheng Lin, Chen-Hua Yu | 2023-12-26 |
| 11854955 | Fan-out package with controllable standoff | Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng | 2023-12-26 |
| 11855017 | Semiconductor device and method | Ting-Li Yang, Ming-Da Cheng, Yung-Han Chuang, Hsueh-Sheng Wang | 2023-12-26 |
| 11855028 | Hybrid micro-bump integration with redistribution layer | Ting-Li Yang, Yi-Wen Wu, Sheng-Pin Yang, Hao-Chun Liu | 2023-12-26 |
| 11848265 | Semiconductor package with improved interposer structure | Yi-Wen Wu, Techi Wong, Po-Yao Chuang, Shih-Ting Hung, Shin-Puu Jeng | 2023-12-19 |
| 11837587 | Package structure and manufacturing method thereof | Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang +2 more | 2023-12-05 |
| 11824007 | Dual-sided routing in 3D SiP structure | Po-Yao Chuang, Meng-Liang Lin, Yi-Wen Wu, Shin-Puu Jeng, Techi Wong | 2023-11-21 |
| 11817437 | Method of forming package structure | Jing-Cheng Lin | 2023-11-14 |