Issued Patents All Time
Showing 25 most recent of 173 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12432964 | Co-integrated gallium nitride (GaN) and complementary metal oxide semiconductor (CMOS) integrated circuit technology | Anand S. Murthy, Robert Ehlert, Han Wui Then, Marko Radosavljevic, Nicole K. Thomas +1 more | 2025-09-30 |
| 12414366 | Co-integration of high voltage (HV) and low voltage (LV) transistor structures, using channel height and spacing modulation | Prashant Majhi, Anand S. Murthy, Rushabh SHAH, Susmita Ghose | 2025-09-09 |
| 12402387 | Integrated circuit structures including a titanium silicide material | Dan S. LAVRIC, Thomas T. TROEGER, Suresh Vishwanath, Jitendra Kumar Jha, John F. Richards +2 more | 2025-08-26 |
| 12342574 | Contact resistance reduction in transistor devices with metallization on both sides | Koustav Ganguly, Ryan Keech, Subrina RAFIQUE, Anand S. Murthy, Ehren Mannebach +2 more | 2025-06-24 |
| 12272688 | Selective growth self-aligned gate endcap (SAGE) architectures without fin end gap | Leonard P. GULER, Zachary Geiger, Szuya S. Liao | 2025-04-08 |
| 12255234 | Integrated circuit structures having germanium-based channels | Siddharth Chouksey, Anand S. Murthy, Harold W. Kennel, Jack T. Kavalieros, Tahir Ghani +2 more | 2025-03-18 |
| 12206027 | Gate-all-around integrated circuit structures having nanowires with tight vertical spacing | Anand S. Murthy, Biswajeet Guha, Tahir Ghani, Susmita Ghose, Zachary Geiger | 2025-01-21 |
| 12191349 | Reducing off-state leakage in semiconductor devices | Dipanjan Basu, Cory E. Weber, Justin R. Weber, Sean T. Ma, Harold W. Kennel +3 more | 2025-01-07 |
| 12166124 | Gate-all-around integrated circuit structures having germanium-doped nanoribbon channel structures | Ryan Murray Hickey, Anand S. Murthy, Rushabh SHAH, Ju H. Nam | 2024-12-10 |
| 12119387 | Low resistance approaches for fabricating contacts and the resulting structures | Gilbert Dewey, Nazila Haratipour, Siddharth Chouksey, Jack T. Kavalieros, Jitendra Kumar Jha +6 more | 2024-10-15 |
| 12046600 | Techniques for achieving multiple transistor fin dimensions on a single die | Anand S. Murthy | 2024-07-23 |
| 12046517 | Self-aligned 3-D epitaxial structures for MOS device fabrication | Daniel B. Aubertine, Anand S. Murthy, Gaurav Thareja, Tahir Ghani | 2024-07-23 |
| 12046654 | Integrated circuit structures including a titanium silicide material | Dan S. LAVRIC, Thomas T. TROEGER, Suresh Vishwanath, Jitendra Kumar Jha, John F. Richards +2 more | 2024-07-23 |
| 12021081 | Techniques for achieving multiple transistor fin dimensions on a single die | Anand S. Murthy | 2024-06-25 |
| 11942526 | Integrated circuit contact structures | Patrick Morrow, Anand S. Murthy, Rishabh Mehandru | 2024-03-26 |
| 11923421 | Integrated circuit structures having germanium-based channels | Siddharth Chouksey, Anand S. Murthy, Harold W. Kennel, Jack T. Kavalieros, Tahir Ghani +2 more | 2024-03-05 |
| 11769836 | Gate-all-around integrated circuit structures having nanowires with tight vertical spacing | Anand S. Murthy, Biswajeet Guha, Tahir Ghani, Susmita Ghose, Zachary Geiger | 2023-09-26 |
| 11764275 | Indium-containing fin of a transistor device with an indium-rich core | Chandra S. Mohapatra, Harold W. Kennel, Anand S. Murthy, Willy Rachmady, Gilbert Dewey +4 more | 2023-09-19 |
| 11757004 | Transistors including source/drain employing double-charge dopants | Anand S. Murthy, Tahir Ghani | 2023-09-12 |
| 11735670 | Non-selective epitaxial source/drain deposition to reduce dopant diffusion for germanium NMOS transistors | Anand S. Murthy, Karthik Jambunathan, Cory Bomberger, Tahir Ghani, Jack T. Kavalieros +3 more | 2023-08-22 |
| 11699756 | Source/drain diffusion barrier for germanium nMOS transistors | Anand S. Murthy, Karthik Jambunathan, Cory Bomberger, Tahir Ghani, Jack T. Kavalieros +3 more | 2023-07-11 |
| 11658217 | Transistors with ion- or fixed charge-based field plate structures | Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Nidhi Nidhi, Paul B. Fischer +3 more | 2023-05-23 |
| 11610995 | Methods of forming dislocation enhanced strain in NMOS and PMOS structures | Michael Jackson, Anand S. Murthy, Saurabh Morarka, Chandra S. Mohapatra | 2023-03-21 |
| 11588017 | Nanowire for transistor integration | Chandra S. Mohapatra, Anand S. Murthy, Karthik Jambunathan | 2023-02-21 |
| 11581406 | Method of fabricating CMOS FinFETs by selectively etching a strained SiGe layer | Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Kelin J. Kuhn +1 more | 2023-02-14 |