Issued Patents All Time
Showing 25 most recent of 99 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12328947 | Substrate-less silicon controlled rectifier (SCR) integrated circuit structures | Rui Ma, Kalyan C. Kolluru, Nicholas A. Thomson, Ayan Kar, Benjamin Orr +3 more | 2025-06-10 |
| 12317590 | Substrate-free integrated circuit structures | Biswajeet Guha, Avyaya Jayanthinarasimham, Ayan Kar, Benjamin Orr, Chung-Hsun Lin +9 more | 2025-05-27 |
| 12166031 | Substrate-less electrostatic discharge (ESD) integrated circuit structures | Biswajeet Guha, Daniel Schulman, William Hsu, Chung-Hsun Lin, Curtis Tsai +1 more | 2024-12-10 |
| 12154898 | Substrate-less vertical diode integrated circuit structures | Avyaya Jayanthinarasimham, Suresh Vishwanath | 2024-11-26 |
| 11869987 | Gate-all-around integrated circuit structures including varactors | Ayan Kar, Saurabh Morarka, Carlos Nieva-Lozano, Kalyan C. Kolluru, Biswajeet Guha +2 more | 2024-01-09 |
| 11417781 | Gate-all-around integrated circuit structures including varactors | Ayan Kar, Saurabh Morarka, Carlos Nieva-Lozano, Kalyan C. Kolluru, Biswajeet Guha +2 more | 2022-08-16 |
| 11404415 | Stacked-gate transistors | Wenjun Li, Tao Chu, Bingwu Liu | 2022-08-02 |
| 10991796 | Source/drain contact depth control | Lin Hu, Veeraraghavan S. Basker, Kai Zhao, Daniel Jaeger, Keith H. Tabakman +1 more | 2021-04-27 |
| 10867912 | Dummy fill scheme for use with passive devices | Jaladhi Mehta, Daniel James Dechene, Ahmed Hassan | 2020-12-15 |
| 10796973 | Test structures connected with the lowest metallization levels in an interconnect structure | Mankyu Yang, Vara Govindeswara Reddy Vakada, Edward P. Maciejewski, Atsushi Ogino, Vikrant Chauhan +1 more | 2020-10-06 |
| 10790204 | Test structure leveraging the lowest metallization level of an interconnect structure | Mankyu Yang, Vara Govindeswara Reddy Vakada, Edward P. Maciejewski, Atsushi Ogino, Vikrant Chauhan +1 more | 2020-09-29 |
| 10672907 | Channel region dopant control in fin field effect transistor | Murshed Chowdhury, Arvind Kumar | 2020-06-02 |
| 10566411 | On-chip resistors with direct wiring connections | Atsushi Ogino, Lin Hu | 2020-02-18 |
| 10269932 | Asymmetric formation of epi semiconductor material in source/drain regions of FinFET devices | Ankur Arya, Qun Gao, Christopher Nassar, Junsic Hong, Vishal Chhabra | 2019-04-23 |
| 10170337 | Implant after through-silicon via (TSV) etch to getter mobile ions | Christopher N. Collins, Mukta G. Farooq, Troy L. Graves-Abe, Robert Hannon, Herbert L. Ho +1 more | 2019-01-01 |
| 10083878 | Fin fabrication process with dual shallow trench isolation and tunable inner and outer fin profile | Shreesh Narasimha | 2018-09-25 |
| 10074571 | Device with decreased pitch contact to active regions | Shreesh Narasimha, Scott R. Stiffler | 2018-09-11 |
| 9991167 | Method and IC structure for increasing pitch between gates | Arvind Kumar, Murshed Chowdhury, Chung-Hsun Lin | 2018-06-05 |
| 9960168 | Capacitor strap connection structure and fabrication method | Veeraraghavan S. Basker, Kangguo Cheng, Benjamin Cipriany, Ramachandra Divakaruni, Ali Khakifirooz +2 more | 2018-05-01 |
| 9780002 | Threshold voltage and well implantation method for semiconductor devices | Xintuo Dai, Mahender Kumar, Daniel James Dechene, Daniel Jaeger | 2017-10-03 |
| 9673197 | FinFET with constrained source-drain epitaxial region | Arvind Kumar, Dan M. Mocuta | 2017-06-06 |
| 9536879 | FinFET with constrained source-drain epitaxial region | Arvind Kumar, Dan M. Mocuta | 2017-01-03 |
| 9536985 | Epitaxial growth of material on source/drain regions of FinFET structure | Michael P. Chudzik, Eric C. Harley, Judson R. Holt, Yue Ke, Rishikesh Krishnan +2 more | 2017-01-03 |
| 9443854 | FinFET with constrained source-drain epitaxial region | Arvind Kumar, Dan M. Mocuta | 2016-09-13 |
| 9437496 | Merged source drain epitaxy | Michael P. Chudzik, Edward P. Maciejewski, Kevin McStay, Shreesh Narasimha, Chengwen Pei +1 more | 2016-09-06 |