Issued Patents All Time
Showing 426–450 of 1,139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10978574 | Floating gate prevention and capacitance reduction in semiconductor devices | Kangguo Cheng, Chanro Park, Juntao Li | 2021-04-13 |
| 10971362 | Extreme ultraviolet patterning process with resist hardening | Chanro Park, Kangguo Cheng, Choonghyun Lee | 2021-04-06 |
| 10964750 | Steep-switch field effect transistor with integrated bi-stable resistive system | Julien Frougier, Nicolas Loubet, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng | 2021-03-30 |
| 10957799 | Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions | Julien Frougier, Chanro Park, Edward J. Nowak, Yi Qi, Kangguo Cheng +1 more | 2021-03-23 |
| 10957544 | Gate cut with high selectivity to preserve interlevel dielectric layer | Andrew M. Greene, Ryan O. Jung | 2021-03-23 |
| 10950692 | Methods of forming air gaps between source/drain contacts and the resulting devices | Vimal Kamineni, Shesh Mani Pandey, Hui Zang | 2021-03-16 |
| 10950610 | Asymmetric gate cut isolation for SRAM | Bipul C. Paul, Julien Frougier, Daniel Chanemougame, Hui Zang | 2021-03-16 |
| 10950506 | Forming single and double diffusion breaks | Juntao Li, Kangguo Cheng, Junli Wang | 2021-03-16 |
| 10950459 | Back end of line structures with metal lines with alternating patterning and metallization schemes | Chanro Park, Chih-Chao Yang, Kangguo Cheng, Juntao Li | 2021-03-16 |
| 10937890 | Vertical field-effect transistor late gate recess process with improved inter-layer dielectric protection | Wenyu Xu, Pietro Montanini, Hemanth Jagannathan | 2021-03-02 |
| 10937786 | Gate cut structures | Hui Zang, Laertis Economikos | 2021-03-02 |
| 10937693 | Methods, apparatus and system for a local interconnect feature over an active region in a finFET device | Andreas Knorr, Haiting Wang, Hui Zang | 2021-03-02 |
| 10935516 | Ion-sensitive field-effect transistor formed with alternating dielectric stack to enhance sensitivity | Kangguo Cheng, Chanro Park, Juntao Li | 2021-03-02 |
| 10930568 | Method and structure to improve overlay margin of non-self-aligned contact in metallization layer | Kangguo Cheng, Chanro Park, Juntao Li | 2021-02-23 |
| 10930510 | Semiconductor device with improved contact resistance and via connectivity | Chanro Park, Kangguo Cheng, Juntao Li | 2021-02-23 |
| 10923590 | Wrap-around contact for vertical field effect transistors | Kangguo Cheng, Chanro Park, Julien Frougier | 2021-02-16 |
| 10923469 | Vertical resistor adjacent inactive gate over trench isolation | Hui Zang, Guowei Xu, Jiehui Shu, Yurong Wen, Garo Derderian +2 more | 2021-02-16 |
| 10923389 | Air-gap spacers for field-effect transistors | Chanro Park, Min Gyu Sung, Hoon Kim | 2021-02-16 |
| 10916650 | Uniform bottom spacer for VFET devices | Steven R. Bentley, Cheng Chi, Chanro Park, Tenko Yamashita | 2021-02-09 |
| 10916630 | Nanosheet devices with improved electrostatic integrity | Chi-Chun Liu, Cheng Chi, Kangguo Cheng | 2021-02-09 |
| 10916478 | Methods of performing fin cut etch processes for FinFET semiconductor devices | Lei Zhuang, Balasubramanian Pranatharthiharan, Lars Liebmann, Terence B. Hook | 2021-02-09 |
| 10916470 | Modified dielectric fill between the contacts of field-effect transistors | Vimal Kamineni, Kangguo Cheng, Adra Carr | 2021-02-09 |
| 10910470 | Nanosheet transistors with inner airgaps | Heng Wu, Alexander Reznicek, Lan Yu | 2021-02-02 |
| 10909443 | Neuromorphic circuit structure and method to form same | Edward J. Nowak, Siva P. Adusumilli, Julien Frougier | 2021-02-02 |
| 10903369 | Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions | Julien Frougier, Chanro Park, Edward J. Nowak, Yi Qi, Kangguo Cheng +1 more | 2021-01-26 |