Issued Patents All Time
Showing 451–475 of 1,139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10903365 | Transistors with uniform source/drain epitaxy | Kangguo Cheng, Chun-Chen Yeh, Tenko Yamashita | 2021-01-26 |
| 10903360 | Vertically integrated memory cells with complementary pass transistor selectors | Bahman Hekmatshoartabari, Alexander Reznicek, Jingyun Zhang | 2021-01-26 |
| 10903317 | Gate-all-around field effect transistors with robust inner spacers and methods | Julien Frougier, Kangguo Cheng, Chanro Park | 2021-01-26 |
| 10903315 | Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection | Nicolas Loubet, Robin Hsin Kuo Chao, Julien Frougier | 2021-01-26 |
| 10900906 | Surface enhanced Raman scattering substrate | Kangguo Cheng, Juntao Li, Chanro Park | 2021-01-26 |
| 10896972 | Self-aligned contact for vertical field effect transistor | Brent A. Anderson, Steven R. Bentley, Su Chen Fan, Balasubramanian Pranatharthiharan, Junli Wang | 2021-01-19 |
| 10896874 | Interconnects separated by a dielectric region formed using removable sacrificial plugs | Guoxiang Ning, Lei Sun | 2021-01-19 |
| 10896845 | Airgap vertical transistor without structural collapse | Kangguo Cheng, Chanro Park, Juntao Li | 2021-01-19 |
| 10892338 | Scaled gate contact and source/drain cap | Hui Zang, Jae Gon Lee | 2021-01-12 |
| 10886378 | Method of forming air-gap spacers and gate contact over active region and the resulting device | Julien Frougier, Chanro Park, Kangguo Cheng | 2021-01-05 |
| 10879073 | Insulating gate separation structure for transistor devices | Chanro Park, Hui Zang, Laertis Economikos, Andre P. Labonte | 2020-12-29 |
| 10879180 | FinFET with etch-selective spacer and self-aligned contact capping layer | Hui Zang, Guowei Xu, Scott Beasor | 2020-12-29 |
| 10872962 | Steep-switch field effect transistor with integrated bi-stable resistive system | Julien Frougier, Nicolas Loubet, Daniel Chanemougame, Ali Razavieh, Kangguo Cheng | 2020-12-22 |
| 10872979 | Spacer structures for a transistor device | Hui Zang, Chung Foong Tan, Guowei Xu, Haiting Wang, Yue Zhong +2 more | 2020-12-22 |
| 10872809 | Contact structures for integrated circuit products | Lars Liebmann, Balasubramanian S. Pranatharthi Haran, Veeraraghavan S. Basker | 2020-12-22 |
| 10854515 | Methods, apparatus, and system for protecting cobalt formations from oxidation during semiconductor device formation | Vimal Kamineni, Mark V. Raymond | 2020-12-01 |
| 10840147 | Fin cut forming single and double diffusion breaks | Juntao Li, Junli Wang, Kangguo Cheng | 2020-11-17 |
| 10840329 | Nanosheet transistor having improved bottom isolation | Kangguo Cheng, Chun-Chen Yeh | 2020-11-17 |
| 10840148 | One-time programmable device compatible with vertical transistor processing | Kangguo Cheng, Juntao Li, Chanro Park | 2020-11-17 |
| 10840146 | Structures and SRAM bit cells with a buried cross-couple interconnect | Bipul C. Paul, Julien Frougier | 2020-11-17 |
| 10832943 | Gate contact over active region with self-aligned source/drain contact | Su Chen Fan, Cheng Chi, Kangguo Cheng | 2020-11-10 |
| 10832947 | Fully aligned via formation without metal recessing | Chanro Park, Kangguo Cheng, Juntao Li | 2020-11-10 |
| 10832944 | Interconnect structure having reduced resistance variation and method of forming same | Nicholas V. LiCausi, Chanro Park, Andre P. Labonte | 2020-11-10 |
| 10833191 | Integrating nanosheet transistors, on-chip embedded memory, and extended-gate transistors on the same substrate | Julien Frougier, Kangguo Cheng, Juntao Li | 2020-11-10 |
| 10832916 | Self-aligned gate isolation with asymmetric cut placement | Carl Radens, Kangguo Cheng, Veeraraghavan S. Basker | 2020-11-10 |