Issued Patents All Time
Showing 501–525 of 1,139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10790148 | Method to increase effective gate height | Heimanu Niebojewski, Andrew M. Greene | 2020-09-29 |
| 10784357 | Fabrication of vertical field effect transistor structure with controlled gate length | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2020-09-22 |
| 10784171 | Vertically stacked complementary-FET device with independent gate control | Julien Frougier, Puneet Harischandra Suvarna | 2020-09-22 |
| 10777465 | Integration of vertical-transport transistors and planar transistors | Chun-Chen Yeh, Kangguo Cheng, Tenko Yamashita | 2020-09-15 |
| 10770388 | Transistor with recessed cross couple for gate contact over active region integration | Veeraraghavan S. Basker, Kangguo Cheng, Jia Zeng, Youngtag Woo, Mahender Kumar +1 more | 2020-09-08 |
| 10770566 | Unique gate cap and gate cap spacer structures for devices on integrated circuit products | Julien Frougier, Chanro Park, Kangguo Cheng | 2020-09-08 |
| 10770454 | On-chip metal-insulator-metal (MIM) capacitor and methods and systems for forming same | Chanro Park, Kangguo Cheng, Juntao Li | 2020-09-08 |
| 10770585 | Self-aligned buried contact for vertical field-effect transistor and method of production thereof | Chanro Park, Andre P. Labonte, Daniel Chanemougame | 2020-09-08 |
| 10770562 | Interlayer dielectric replacement techniques with protection for source/drain contacts | Kangguo Cheng, Juntao Li, Andrew M. Greene, Vimal Kamineni, Adra Carr +1 more | 2020-09-08 |
| 10763342 | Semiconductor devices having equal thickness gate spacers | Cheng Chi | 2020-09-01 |
| 10756203 | Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism | Julien Frougier, Steven R. Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini | 2020-08-25 |
| 10756096 | Integrated circuit structure with complementary field effect transistor and buried metal interconnect and method | Bipul C. Paul | 2020-08-25 |
| 10749038 | Width adjustment of stacked nanowires | Kangguo Cheng, Xin Miao, Tenko Yamashita | 2020-08-18 |
| 10749031 | Large area contacts for small transistors | Xiuyu Cai, Qing Liu, Chun-Chen Yeh | 2020-08-18 |
| 10746691 | Ion-sensitive field effect transistor (ISFET) with enhanced sensitivity | Kangguo Cheng, Chanro Park, Juntao Li | 2020-08-18 |
| 10741675 | Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism | Julien Frougier, Steven R. Bentley, Kangguo Cheng, Nicolas Loubet, Pietro Montanini | 2020-08-11 |
| 10741668 | Short channel and long channel devices | Bala Haran, Balaji Kannan, Katsunori Onishi, Vimal Kamineni | 2020-08-11 |
| 10741656 | Wraparound contact surrounding source/drain regions of integrated circuit structures and method of forming same | Hui Zang, Shesh Mani Pandey, Laertis Economikos | 2020-08-11 |
| 10741639 | Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection | Nicolas Loubet, Robin Hsin Kuo Chao, Julien Frougier | 2020-08-11 |
| 10741451 | FinFET having insulating layers between gate and source/drain contacts | Hui Zang, Laertis Economikos, Shesh Mani Pandey, Chanro Park | 2020-08-11 |
| 10734525 | Gate-all-around transistor with spacer support and methods of forming same | Julien Frougier, Christopher M. Prindle, Nigel G. Cave | 2020-08-04 |
| 10734499 | Unmerged epitaxial process for FinFET devices with aggressive fin pitch scaling | Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Tenko Yamashita | 2020-08-04 |
| 10727308 | Gate contact structure for a transistor | Hao Tang, Cheng Chi, Daniel Chanemougame, Lars Liebmann, Mark V. Raymond | 2020-07-28 |
| 10727136 | Integrated gate contact and cross-coupling contact formation | Hui Zang, Chanro Park, Laertis Economikos | 2020-07-28 |
| 10727120 | Controlling back-end-of-line dimensions of semiconductor devices | Sean Xuan Lin, Guoxiang Ning, Lei Sun | 2020-07-28 |