Issued Patents All Time
Showing 476–500 of 1,139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10832954 | Forming a reliable wrap-around contact without source/drain sacrificial regions | Julien Frougier, Kangguo Cheng | 2020-11-10 |
| 10833191 | Integrating nanosheet transistors, on-chip embedded memory, and extended-gate transistors on the same substrate | Julien Frougier, Kangguo Cheng, Juntao Li | 2020-11-10 |
| 10832964 | Replacement contact formation for gate contact over active region with selective metal growth | Balasubramanian Pranatharthiharan, Chanro Park, Nicolas Loubet | 2020-11-10 |
| 10833198 | Confined source drain epitaxy to reduce shorts in CMOS integrated circuits | Chun-Chen Yeh, Lan Yu, Alexander Reznicek | 2020-11-10 |
| 10832967 | Tapered fin-type field-effect transistors | Hui Zang, Garo Derderian | 2020-11-10 |
| 10825741 | Methods of forming single diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products | Hui Zang | 2020-11-03 |
| 10825913 | Methods, apparatus, and manufacturing system for FinFET devices with reduced parasitic capacitance | Hui Zang, Haiting Wang | 2020-11-03 |
| 10818773 | Trench silicide contacts with high selectivity process | Andrew M. Greene, Balasubramanian Pranatharthiharan | 2020-10-27 |
| 10818776 | Nanosheet transistor with optimized junction and cladding detectivity control | Kangguo Cheng, Nicolas Loubet, Tenko Yamashita, Chun-Chen Yeh | 2020-10-27 |
| 10818674 | Structures and SRAM bit cells integrating complementary field-effect transistors | Randy W. Mann, Bipul C. Paul, Julien Frougier | 2020-10-27 |
| 10818792 | Nanosheet field-effect transistors formed with sacrificial spacers | Julien Frougier, Daniel Chanemougame | 2020-10-27 |
| 10811319 | Middle of line structures | Hui Zang | 2020-10-20 |
| 10804398 | Method of forming wrap-around-contact and the resulting device | Julien Frougier | 2020-10-13 |
| 10804148 | Buried contact to provide reduced VFET feature-to-feature tolerance requirements | Su Chen Fan, Jeffrey C. Shearer, Robert C. Wong | 2020-10-13 |
| 10804199 | Self-aligned chamferless interconnect structures of semiconductor devices | Yongjun Shi, Nan Fu, Chun Yu Wong | 2020-10-13 |
| 10804379 | FinFET device and method of manufacturing | Hui Zang, Scott Beasor | 2020-10-13 |
| 10804136 | Fin structures with bottom dielectric isolation | Kangguo Cheng, Chun-Chen Yeh, Tenko Yamashita | 2020-10-13 |
| 10796957 | Buried contact to provide reduced VFET feature-to-feature tolerance requirements | Su Chen Fan, Jeffrey C. Shearer, Robert C. Wong | 2020-10-06 |
| 10797049 | FinFET structure with dielectric bar containing gate to reduce effective capacitance, and method of forming same | Hui Zang, Haiting Wang, Chung Foong Tan, Guowei Xu, Scott Beasor +1 more | 2020-10-06 |
| 10797154 | Trench silicide contacts with high selectivity process | Andrew M. Greene, Balasubramanian Pranatharthiharan | 2020-10-06 |
| 10790395 | finFET with improved nitride to fin spacing | Injo Ok, Chanro Park, Min Gyu Sung | 2020-09-29 |
| 10790379 | Vertical field effect transistor with anchor | Juntao Li, Kangguo Cheng | 2020-09-29 |
| 10788446 | Ion-sensitive field-effect transistor with micro-pillar well to enhance sensitivity | Juntao Li, Kangguo Cheng, Chanro Park | 2020-09-29 |
| 10790148 | Method to increase effective gate height | Heimanu Niebojewski, Andrew M. Greene | 2020-09-29 |
| 10790363 | IC structure with metal cap on cobalt layer and methods of forming same | Laertis Economikos, Kevin J. Ryan, Hui Zang | 2020-09-29 |