Issued Patents All Time
Showing 526–550 of 1,139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10720391 | Method of forming a buried interconnect and the resulting devices | Bipul C. Paul, Lars Liebmann | 2020-07-21 |
| 10714591 | Gate structure for a transistor device with a novel pillar structure positioned thereabove | Youngtag Woo, Hui Zang | 2020-07-14 |
| 10714567 | Nanosheet field-effect transistor with substrate isolation | Julien Frougier | 2020-07-14 |
| 10714470 | Method and apparatus of forming high voltage varactor and vertical transistor on a substrate | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2020-07-14 |
| 10707218 | Two port SRAM cell using complementary nano-sheet/wire transistor devices | Bipul C. Paul | 2020-07-07 |
| 10707206 | Gate cut isolation formed as layer against sidewall of dummy gate mandrel | Hui Zang, Laertis Economikos | 2020-07-07 |
| 10700173 | FinFET device with a wrap-around silicide source/drain contact structure | Yi Qi, Hsien-Ching Lo, Hong Yu, Yanping Shen, Wei Hong +4 more | 2020-06-30 |
| 10699965 | Removal of epitaxy defects in transistors | Andrew M. Greene, Christopher M. Prindle, Pietro Montanini | 2020-06-30 |
| 10699957 | Late gate cut using selective dielectric deposition | Hui Zang, Jiehui Shu, Chanro Park, Laertis Economikos | 2020-06-30 |
| 10699942 | Vertical-transport field-effect transistors having gate contacts located over the active region | Chanro Park, Daniel Chanemougame, Steven R. Soss, Lars Liebmann, Hui Zang +1 more | 2020-06-30 |
| 10692991 | Gate-all-around field effect transistors with air-gap inner spacers and methods | Daniel Chanemougame, Julien Frougier | 2020-06-23 |
| 10685874 | Self-aligned cuts in an interconnect structure | Hui Zang, Lei Sun, Lars Liebmann, Daniel Chanemougame, Guillaume Bouche | 2020-06-16 |
| 10685872 | Electrically isolated contacts in an active region of a semiconductor device | Kangguo Cheng, Peng Xu, Ekmini Anuja De Silva | 2020-06-16 |
| 10680081 | Vertical transistors with improved top source/drain junctions | Kangguo Cheng, Muthumanickam Sankarapandian, Tenko Yamashita, Chun-Chen Yeh | 2020-06-09 |
| 10680064 | Techniques for VFET top source/drain epitaxy | Kangguo Cheng, Cheng Chi, Chi-Chun Liu, Tenko Yamashita, Chun-Chen Yeh | 2020-06-09 |
| 10679906 | Method of forming nanosheet transistor structures with reduced parasitic capacitance and improved junction sharpness | Kangguo Cheng, Chanro Park, Tenko Yamashita | 2020-06-09 |
| 10679894 | Airgap spacers formed in conjunction with a late gate cut | Julien Frougier, Chanro Park, Kangguo Cheng | 2020-06-09 |
| 10665692 | Non-self aligned gate contacts formed over the active region of a transistor | Chanro Park, Kangguo Cheng, Julien Frougier | 2020-05-26 |
| 10665669 | Insulative structure with diffusion break integral with isolation layer and methods to form same | Julien Frougier | 2020-05-26 |
| 10665590 | Wrap-around contact surrounding epitaxial regions of integrated circuit structures and method of forming same | William J. Taylor, Jr., Hui Zang | 2020-05-26 |
| 10665586 | Method of concurrently forming source/drain and gate contacts and related device | Cheng Chi | 2020-05-26 |
| 10665505 | Self-aligned gate contact isolation | Kangguo Cheng, Peng Xu, Ekmini Anuja De Silva | 2020-05-26 |
| 10658459 | Nanosheet transistor with robust source/drain isolation from substrate | Robin Hsin Kuo Chao, Kangguo Cheng, Cheng Chi, John H. Zhang | 2020-05-19 |
| 10658243 | Method for forming replacement metal gate and related structures | Daniel Chanemougame, Steven R. Soss, Steven Bentley, Chanro Park | 2020-05-19 |
| 10651291 | Inner spacer formation in a nanosheet field-effect transistor | Julien Frougier | 2020-05-12 |