Issued Patents All Time
Showing 551–575 of 1,139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10651284 | Methods of forming gate contact structures and cross-coupled contact structures for transistor devices | Youngtag Woo, Daniel Chanemougame, Bipul C. Paul, Lars Liebmann, Heimanu Niebojewski +3 more | 2020-05-12 |
| 10651173 | Single diffusion cut for gate structures | Guowei Xu, Hui Zang, Haiting Wang | 2020-05-12 |
| 10643845 | Repaired mask structures and resultant underlying patterned structures | Xunyuan Zhang, Yi Qi | 2020-05-05 |
| 10644157 | Fin-type field effect transistors with uniform channel lengths and below-channel isolation on bulk semiconductor substrates and methods | Julien Frougier, Andreas Knorr, Srikanth B. Samavedam | 2020-05-05 |
| 10636890 | Chamfered replacement gate structures | Haiting Wang, Rongtao Lu, Chih-Chiang Chang, Guowei Xu, Hui Zang +1 more | 2020-04-28 |
| 10636694 | Dielectric isolation in gate-all-around devices | Robin Hsin Kuo Chao, Kangguo Cheng, Nicolas Loubet, Pietro Montanini | 2020-04-28 |
| 10629516 | Hybrid dual damascene structures with enlarged contacts | Daniel Chanemougame, Julien Frougier | 2020-04-21 |
| 10629743 | Semiconductor structure including low-K spacer material | Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz | 2020-04-21 |
| 10629739 | Methods of forming spacers adjacent gate structures of a transistor device | Hui Zang, Chung Foong Tan, Guowei Xu, Haiting Wang, Yue Zhong +2 more | 2020-04-21 |
| 10629707 | FinFET structure with bulbous upper insulative cap portion to protect gate height, and related method | Hui Zang, Jiehui Shu | 2020-04-21 |
| 10629701 | Self-aligned gate cut method and multilayer gate-cut pillar structure | Youngtag Woo, Hui Zang | 2020-04-21 |
| 10629699 | Gate height control and ILD protection | Andrew M. Greene, John R. Sporre, Stan Tsai | 2020-04-21 |
| 10629694 | Gate contact and cross-coupling contact formation | Hui Zang, Haiting Wang, Scott Beasor | 2020-04-21 |
| 10627720 | Overlay mark structures | Lei Sun, John H. Zhang, Shao Beng Law, Guoxiang Ning, Xunyuan Zhang | 2020-04-21 |
| 10622475 | Uniform bottom spacer for VFET devices | Steven R. Bentley, Cheng Chi, Chanro Park, Tenko Yamashita | 2020-04-14 |
| 10622457 | Forming replacement low-K spacer in tight pitch fin field effect transistors | Xiuyu Cai, Chun-Chen Yeh, Qing Liu | 2020-04-14 |
| 10622458 | Self-aligned contact for vertical field effect transistor | Brent A. Anderson, Steven R. Bentley, Su Chen Fan, Balasubramanian Pranatharthiharan, Junli Wang | 2020-04-14 |
| 10622357 | FinFET including tunable fin height and tunable fin width ratio | Xiuyu Cai, Qing Liu, Chun-Chen Yeh | 2020-04-14 |
| 10622260 | Vertical transistor with reduced parasitic capacitance | Chanro Park, Kangguo Cheng | 2020-04-14 |
| 10615277 | VFET CMOS dual epitaxy integration | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2020-04-07 |
| 10607893 | Middle of line structures | Hui Zang | 2020-03-31 |
| 10608082 | Field-effect transistors including multiple gate lengths | Julien Frougier | 2020-03-31 |
| 10600914 | Isolation pillar first gate structures and methods of forming same | Wei Zhao, Ming Hao Tang, Haiting Wang, Rui Chen, Yuping Ren +2 more | 2020-03-24 |
| 10600778 | Method and apparatus of forming high voltage varactor and vertical transistor on a substrate | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2020-03-24 |
| 10593757 | Integrated circuits having converted self-aligned epitaxial etch stop | Jiehui Shu, Hui Zang, Haiting Wang | 2020-03-17 |