Issued Patents All Time
Showing 51–75 of 128 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10998314 | Gate cut with integrated etch stop layer | Marc A. Bergendahl, Rajasekhar Venigalla | 2021-05-04 |
| 10985076 | Single metallization scheme for gate, source, and drain contact integration | Victor Chan, Gangadhara Raja Muthinti | 2021-04-20 |
| 10985250 | Gate cut device fabrication with extended height gates | Kangguo Cheng, John R. Sporre, Peng Xu | 2021-04-20 |
| 10985260 | Trench silicide contacts with high selectivity process | Balasubramanian Pranatharthiharan, Ruilong Xie | 2021-04-20 |
| 10957544 | Gate cut with high selectivity to preserve interlevel dielectric layer | Ryan O. Jung, Ruilong Xie | 2021-03-23 |
| 10943990 | Gate contact over active enabled by alternative spacer scheme and claw-shaped cap | Victor Chan, Gangadhara Raja Muthinti, Veeraraghavan S. Basker, Junli Wang, Kisik Choi +1 more | 2021-03-09 |
| 10923401 | Gate cut critical dimension shrink and active gate defect healing using selective deposition | Marc A. Bergendahl, Ekmini Anuja De Silva, Alex Joseph Varghese, Yann Mignot, Matthew T. Shoudy +2 more | 2021-02-16 |
| 10903111 | Semiconductor device with linerless contacts | Alex Joseph Varghese, Marc A. Bergendahl, Dallas Lea, Matthew T. Shoudy, Yann Mignot +2 more | 2021-01-26 |
| 10892181 | Semiconductor device with mitigated local layout effects | Huimei Zhou, Gen Tsutsui, Veeraraghavan S. Basker, Dechao Guo, Huiming Bu +1 more | 2021-01-12 |
| 10840345 | Source and drain contact cut last process to enable wrap-around-contact | Dechao Guo, Tenko Yamashita, Veeraraghavan S. Basker, Robert R. Robison, Ardasheir Rahman | 2020-11-17 |
| 10818773 | Trench silicide contacts with high selectivity process | Balasubramanian Pranatharthiharan, Ruilong Xie | 2020-10-27 |
| 10797154 | Trench silicide contacts with high selectivity process | Balasubramanian Pranatharthiharan, Ruilong Xie | 2020-10-06 |
| 10790148 | Method to increase effective gate height | Heimanu Niebojewski, Ruilong Xie | 2020-09-29 |
| 10790372 | Direct gate metal cut using selective deposition to protect the gate end line from metal shorts | Ekmini Anuja De Silva | 2020-09-29 |
| 10790393 | Utilizing multilayer gate spacer to reduce erosion of semiconductor Fin during spacer patterning | Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Eric R. Miller, Pietro Montanini | 2020-09-29 |
| 10770562 | Interlayer dielectric replacement techniques with protection for source/drain contacts | Kangguo Cheng, Juntao Li, Vimal Kamineni, Adra Carr, Chanro Park +1 more | 2020-09-08 |
| 10741673 | Controlling gate profile by inter-layer dielectric (ILD) nanolaminates | Michael P. Belyansky, Fee Li Lie, Huimei Zhou | 2020-08-11 |
| 10734234 | Metal cut patterning and etching to minimize interlayer dielectric layer loss | Kisup Chung, Ekmini Anuja De Silva, Siva Kanakasabapathy, Indira Seshadri | 2020-08-04 |
| 10699965 | Removal of epitaxy defects in transistors | Ruilong Xie, Christopher M. Prindle, Pietro Montanini | 2020-06-30 |
| 10692990 | Gate cut in RMG | Ruqiang Bao, Siva Kanakasabapathy | 2020-06-23 |
| 10685866 | Fin isolation to mitigate local layout effects | Huimei Zhou, Gen Tsutsui, Dechao Guo, Huiming Bu, Robert R. Robison +2 more | 2020-06-16 |
| 10672910 | Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT) | Huimei Zhou, Ruqiang Bao, Michael P. Belyansky, Gen Tsutsui | 2020-06-02 |
| 10665589 | Gate cut with integrated etch stop layer | Marc A. Bergendahl, Rajasekhar Venigalla | 2020-05-26 |
| 10658473 | Gate cut device fabrication with extended height gates | Kangguo Cheng, John R. Sporre, Peng Xu | 2020-05-19 |
| 10658224 | Method of fin oxidation by flowable oxide fill and steam anneal to mitigate local layout effects | Huimei Zhou, Gen Tsutsui, Veeraraghavan S. Basker, Dechao Guo, Huiming Bu +1 more | 2020-05-19 |