Issued Patents All Time
Showing 101–125 of 128 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10186599 | Forming self-aligned contact with spacer first | Su Chen Fan, Sean Lian, Balasubramanian Pranatharthiharan, Mark V. Raymond, Ruilong Xie | 2019-01-22 |
| 10177240 | FinFET device formed by a replacement metal-gate method including a gate cut-last step | Balasubramanian Pranatharthi Haran, Injo Ok, Charan V. Surisetty | 2019-01-08 |
| 10177039 | Shallow trench isolation structures and contact patterning | Ravikumar Ramachandran, Rajasekhar Venigalla | 2019-01-08 |
| 10128238 | Integrated circuit having oxidized gate cut region and method to fabricate same | Kangguo Cheng, Peng Xu | 2018-11-13 |
| 10128239 | Preserving channel strain in fin cuts | Dechao Guo, Ravikumar Ramachandran, Rajasekhar Venigalla | 2018-11-13 |
| 10083861 | HDP fill with reduced void formation and spacer damage | Huiming Bu, Balasubramanian Pranatharthiharan, Ruilong Xie | 2018-09-25 |
| 10083961 | Gate cut with integrated etch stop layer | Marc A. Bergendahl, Rajasekhar Venigalla | 2018-09-25 |
| 10079287 | Gate cut device fabrication with extended height gates | Kangguo Cheng, John R. Sporre, Peng Xu | 2018-09-18 |
| 10002792 | HDP fill with reduced void formation and spacer damage | Huiming Bu, Balasubramanian Pranatharthiharan, Ruilong Xie | 2018-06-19 |
| 9935003 | HDP fill with reduced void formation and spacer damage | Huiming Bu, Balasubramanian Pranatharthiharan, Ruilong Xie | 2018-04-03 |
| 9929057 | HDP fill with reduced void formation and spacer damage | Huiming Bu, Balasubramanian Pranatharthiharan, Ruilong Xie | 2018-03-27 |
| 9923080 | Gate height control and ILD protection | John R. Sporre, Stan Tsai, Ruilong Xie | 2018-03-20 |
| 9923078 | Trench silicide contacts with high selectivity process | Balasubramanian Pranatharthiharan, Ruilong Xie | 2018-03-20 |
| 9911823 | POC process flow for conformal recess fill | Sanjay C. Mehta, Balasubramanian Pranatharthiharan, Ruilong Xie | 2018-03-06 |
| 9837276 | Gate cut with high selectivity to preserve interlevel dielectric layer | Ryan O. Jung, Ruilong Xie | 2017-12-05 |
| 9773885 | Self aligned gate shape preventing void formation | Qing Liu, Ruilong Xie, Chun-Chen Yeh | 2017-09-26 |
| 9741823 | Fin cut during replacement gate formation | Balasubramanian Pranatharthiharan, Sivananda K. Kanakasabapathy, John R. Sporre | 2017-08-22 |
| 9721834 | HDP fill with reduced void formation and spacer damage | Huiming Bu, Balasubramanian Pranatharthiharan, Ruilong Xie | 2017-08-01 |
| 9721848 | Cutting fins and gates in CMOS devices | Huiming Bu, Kangguo Cheng, Dechao Guo, Sivananda K. Kanakasabapathy, Gauri Karve +6 more | 2017-08-01 |
| 9698101 | Self-aligned local interconnect technology | Injo Ok, Balasubramanian Pranatharthiharan, Charan V. V. S. Surisetty, Ruilong Xie | 2017-07-04 |
| 9659786 | Gate cut with high selectivity to preserve interlevel dielectric layer | Ryan O. Jung, Ruilong Xie | 2017-05-23 |
| 9640633 | Self aligned gate shape preventing void formation | Qing Liu, Ruilong Xie, Chun-Chen Yeh | 2017-05-02 |
| 9634110 | POC process flow for conformal recess fill | Sanjay C. Mehta, Balasubramanian Pranatharthiharan, Ruilong Xie | 2017-04-25 |
| 9601366 | Trench formation for dielectric filled cut region | Ryan O. Jung, Ruilong Xie, Peng Xu | 2017-03-21 |
| 9601335 | Trench formation for dielectric filled cut region | Ryan O. Jung, Ruilong Xie, Peng Xu | 2017-03-21 |