Issued Patents All Time
Showing 76–100 of 128 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10644129 | Gate cut in RMG | Ruqiang Bao, Siva Kanakasabapathy | 2020-05-05 |
| 10629699 | Gate height control and ILD protection | John R. Sporre, Stan Tsai, Ruilong Xie | 2020-04-21 |
| 10622352 | Fin cut to prevent replacement gate collapse on STI | Balasubramanian Pranatharthiharan, Sivananda K. Kanakasabapathy, John R. Sporre | 2020-04-14 |
| 10622482 | Gate cut using selective deposition to prevent oxide loss | Ekmini Anuja De Silva, Siva Kanakasabapathy | 2020-04-14 |
| 10600884 | Additive core subtractive liner for metal cut etch processes | Ruqiang Bao, Kisup Chung, Sivananda K. Kanakasabapathy, David L. Rath, Indira Seshadri +1 more | 2020-03-24 |
| 10600868 | FinFET gate cut after dummy gate removal | John R. Sporre, Siva Kanakasabapathy, Jeffrey C. Shearer, Nicole Saulnier | 2020-03-24 |
| 10586706 | Gate cut with high selectivity to preserve interlevel dielectric layer | Ryan O. Jung, Ruilong Xie | 2020-03-10 |
| 10580773 | Gate cut with integrated etch stop layer | Marc A. Bergendahl, Rajasekhar Venigalla | 2020-03-03 |
| 10573646 | Preserving channel strain in fin cuts | Dechao Guo, Ravikumar Ramachandran, Rajasekhar Venigalla | 2020-02-25 |
| 10553700 | Gate cut in RMG | Ruqiang Bao, Siva Kanakasabapathy | 2020-02-04 |
| 10541308 | Gate cut device fabrication with extended height gates | Kangguo Cheng, John R. Sporre, Peng Xu | 2020-01-21 |
| 10504798 | Gate cut in replacement metal gate process | Ruilong Xie, Chanro Park, Laertis Economikos, Siva Kanakasabapathy, John R. Sporre | 2019-12-10 |
| 10505016 | Self aligned gate shape preventing void formation | Qing Liu, Ruilong Xie, Chun-Chen Yeh | 2019-12-10 |
| 10381458 | Semiconductor device replacement metal gate with gate cut last in RMG | Balasubramanian Pranatharthi Haran, Injo Ok, Charan V. Surisetty | 2019-08-13 |
| 10347540 | Gate cut using selective deposition to prevent oxide loss | Ekmini Anuja De Silva, Siva Kanakasabapathy | 2019-07-09 |
| 10325848 | Self-aligned local interconnect technology | Injo Ok, Balasubramanian Pranatharthiharan, Charan V. V. S. Surisetty, Ruilong Xie | 2019-06-18 |
| 10297506 | HDP fill with reduced void formation and spacer damage | Huiming Bu, Balasubramanian Pranatharthiharan, Ruilong Xie | 2019-05-21 |
| 10256238 | Preserving channel strain in fin cuts | Dechao Guo, Ravikumar Ramachandran, Rajasekhar Venigalla | 2019-04-09 |
| 10249730 | Controlling gate profile by inter-layer dielectric (ILD) nanolaminates | Michael P. Belyansky, Fee Li Lie, Huimei Zhou | 2019-04-02 |
| 10243079 | Utilizing multilayer gate spacer to reduce erosion of semiconductor fin during spacer patterning | Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Eric R. Miller, Pietro Montanini | 2019-03-26 |
| 10242981 | Fin cut during replacement gate formation | Balasubramanian Pranatharthiharan, Sivananda K. Kanakasabapathy, John R. Sporre | 2019-03-26 |
| 10242918 | Shallow trench isolation structures and contact patterning | Ravikumar Ramachandran, Rajasekhar Venigalla | 2019-03-26 |
| 10236253 | Self-aligned local interconnect technology | Injo Ok, Balasubramanian Pranatharthiharan, Charan V. V. S. Surisetty, Ruilong Xie | 2019-03-19 |
| 10229854 | FinFET gate cut after dummy gate removal | John R. Sporre, Siva Kanakasabapathy, Jeffrey C. Shearer, Nicole Saulnier | 2019-03-12 |
| 10224326 | Fin cut during replacement gate formation | Balasubramanian Pranatharthiharan, Sivananda K. Kanakasabapathy, John R. Sporre | 2019-03-05 |