Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
BD

Bruce B. Doris

Globalfoundries: 70 patents #24 of 4,424Top 1%
SSStmicroelectronics Sa: 33 patents #26 of 1,676Top 2%
CEA: 10 patents #375 of 7,956Top 5%
RERenesas Electronics: 4 patents #1,016 of 4,529Top 25%
TETessera: 4 patents #104 of 271Top 40%
GUGlobalfoundries U.S.: 1 patents #22 of 211Top 15%
ASAdeia Semiconductor Solutions: 1 patents #22 of 57Top 40%
IBInternational Business: 1 patents #4 of 119Top 4%
Motorola: 1 patents #6,475 of 12,470Top 55%
AMD: 1 patents #5,683 of 9,279Top 65%
Hartsdale, NY: #1 of 164 inventorsTop 1%
New York: #9 of 115,490 inventorsTop 1%
Overall (All Time): #118 of 4,157,543Top 1%
767 Patents All Time

Issued Patents All Time

Showing 601–625 of 767 patents

Patent #TitleCo-InventorsDate
8008724 Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers Haining Yang, Huilong Zhu 2011-08-30
8003455 Implantation using a hardmask Kangguo Cheng, Ying Zhang 2011-08-23
7999323 Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices Eduard A. Cartier, Matthew W. Copel, Rajarao Jammy, Young-Hee Kim, Barry P. Linder +3 more 2011-08-16
7993999 High-K/metal gate CMOS finFET with improved pFET threshold voltage Veeraraghavan S. Basker, Kangguo Cheng, Johnathan E. Faltermeier, Ali Khakifirooz 2011-08-09
7989291 Anisotropic stress generation by stress-generating liners having a sublithographic width Lawrence A. Clevenger, Elbert E. Huang, Sampath Purushothaman, Carl Radens 2011-08-02
7960790 Self-aligned planar double-gate transistor structure Omer H. Dokumaci, Kathryn Guarini, Suryanararyan G. Hegde, Meikei Ieong, Erin C. Jones 2011-06-14
7935588 Enhanced transistor performance by non-conformal stressed layers Xiao Hu Liu 2011-05-03
7923782 Hybrid SOI/bulk semiconductor transistors Huilong Zhu, Philip J. Oldiges, Xinlin Wang, Oleg Gluschenkov, Huajie Chen +1 more 2011-04-12
7883944 Ultra-thin semiconductor on insulator metal gate complementary field effect transistor with metal gate and method of forming thereof Huilong Zhu, Philip J. Oldiges 2011-02-08
7880243 Simple low power circuit structure with metal gate and high-k dielectric Eduard A. Cartier, Barry P. Linder, Vijay Narayanan, Vamsi K. Paruchuri 2011-02-01
7872317 Dual metal gate self-aligned integration Alessandro C. Callegari, Michael P. Chudzik, Vijay Narayanan, Vamsi K. Paruchuri, Michelle L. Steen 2011-01-18
7863124 Residue free patterned layer formation method applicable to CMOS structures Michael P. Chudzik, William K. Henson, Hongwen Yan, Ying Zhang 2011-01-04
7847356 Metal gate high-K devices having a layer comprised of amorphous silicon Tze-Chiang Chen, Vijay Narayanan, Vamsi K. Paruchuri 2010-12-07
7847357 High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same Thomas W. Dyer, David R. Medeiros, Anna W. Topol 2010-12-07
7847358 High performance strained CMOS devices Oleg Gluschenkov 2010-12-07
7833849 Method of fabricating a semiconductor structure including one device region having a metal gate electrode located atop a thinned polygate electrode Alessandro C. Callegari, Tze-Chiang Chen, Michael P. Chudzik, Young-Hee Kim, Vijay Narayanan +3 more 2010-11-16
7833891 Semiconductor device manufacturing method using oxygen diffusion barrier layer between buried oxide layer and high K dielectric layer Kagguo Cheng 2010-11-16
7820555 Method of patterning multilayer metal gate structures for CMOS devices Richard S. Wise, Hongwen Yan, Ying Zhang 2010-10-26
7820552 Advanced high-k gate stack patterning and structure containing a patterned high-k gate stack Siva Kanakasabapathy, Ying Zhang, Edmund M. Sikorski, Hongwen Yan, Vijay Narayanan +1 more 2010-10-26
7808020 Self-assembled sidewall spacer Carl Radens 2010-10-05
7807525 Low power circuit structure with metal gate and high-k dielectric Eduard A. Cartier, Barry P. Linder, Vijay Narayanan, Vamsi K. Paruchuri 2010-10-05
7800152 Methods for manufacturing a finfet using a conventional wafer and apparatus manufactured therefrom Huilong Zhu 2010-09-21
7790541 Method and structure for forming multiple self-aligned gate stacks for logic devices Mahender Kumar, Werner Rausch, Robin Van Den Nieuwenhuizen 2010-09-07
7790592 Method to fabricate metal gate high-k devices Tze-Chiang Chen, Vijay Narayanan, Vamsi K. Paruchuri 2010-09-07
7790593 Method for tuning epitaxial growth by interfacial doping and structure including same Katherina Babich, David R. Medeiros, Devendra K. Sadana 2010-09-07