Issued Patents All Time
Showing 26–50 of 159 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7972948 | Method for forming bit lines for semiconductor devices | Weidong Qian, Tazrien Kamal | 2011-07-05 |
| 7964905 | Anti-reflective interpoly dielectric | Robert B. Ogle, Marina V. Plat | 2011-06-21 |
| 7811915 | Method for forming bit lines for semiconductor devices | Weidong Qian, Tazrien Kamal | 2010-10-12 |
| 7786003 | Buried silicide local interconnect with sidewall spacers and method for making the same | Arvind Halliyal, Zoran Krivokapic, Matthew S. Buynoski, Nicholas H. Tripsas, Minh Van Ngo +2 more | 2010-08-31 |
| 7670936 | Nitridation of gate oxide by laser processing | Arvind Halliyal, Nicholas H. Tripsas | 2010-03-02 |
| 7507661 | Method of forming narrowly spaced flash memory contact openings and lithography masks | Emmanuil H. Lingunis, Ning Cheng, Kouros Ghandehari, Anna M. Minvielle, Hung-Eil Kim | 2009-03-24 |
| 7432178 | Bit line implant | Angela T. Hui, Jean Y. Yang, Yu Sun, Weidong Qian | 2008-10-07 |
| 7414277 | Memory cell having combination raised source and drain and method of fabricating same | Ashot Melik-Martirosian, Takashi Orimoto | 2008-08-19 |
| 7394125 | Recessed channel with separated ONO memory device | Jaeyong Park, Hidehiko Shiraiwa, Satoshi Torii | 2008-07-01 |
| 7256141 | Interface layer between dual polycrystalline silicon layers | Weidong Qian, Mark S. Chang, Eric N. Paton | 2007-08-14 |
| 7176113 | LDC implant for mirrorbit to improve Vt roll-off and form sharper junction | Nga-Ching Wong, Weidong Qian, Sameer Haddad, Mark Randolph, Tazrien Kamal | 2007-02-13 |
| 7163860 | Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device | Tazrien Kamal, Yun Wu, Jean Y. Yang, Arvind Halliyal, Rinji Sugino +2 more | 2007-01-16 |
| 7157335 | Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi bit memory devices | Ning Cheng, Minh Van Ngo, Hirokazu Tokuno, Lu You, Angela T. Hui +3 more | 2007-01-02 |
| 7115469 | Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process | Arvind Halliyal, Hidehiko Shiraiwa, Jean Y. Yang | 2006-10-03 |
| 7067377 | Recessed channel with separated ONO memory device | Jaeyong Park, Hidehiko Shiraiwa, Satoshi Torii | 2006-06-27 |
| 7060554 | PECVD silicon-rich oxide layer for reduced UV charging | Minh Van Ngo, Tazrien Kamal, Pei-Yuan Gao | 2006-06-13 |
| 7053446 | Memory wordline spacer | Kashmir Sahota, Tazrien Kamal | 2006-05-30 |
| 7033957 | ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices | Hidehiko Shiraiwa, Tazrien Kamal, Inkuk Kang, Jaeyong Park, Rinji Sugino +4 more | 2006-04-25 |
| 7018896 | UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing | Minh Van Ngo, Tazrien Kamal, Arvind Halliyal, Jaeyong Park, Ning Cheng +6 more | 2006-03-28 |
| 7018868 | Disposable hard mask for memory bitline scaling | Jean Y. Yang, Jeff P. Erhardt, Cyrus E. Tabery, Weidong Qian, Jaeyong Park +1 more | 2006-03-28 |
| 7012008 | Dual spacer process for non-volatile memory devices | Jeffrey A. Shields, Tuan Pham, Yu Sun, Angela T. Hui, Maria C. Chan | 2006-03-14 |
| 7001814 | Laser thermal annealing methods for flash memory devices | Arvind Halliyal, Robert B. Ogle | 2006-02-21 |
| 7001807 | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same | Wei Zheng, Mark Randolph, Nicholas H. Tripsas, Zoran Krivokapic, Jack F. Thomas | 2006-02-21 |
| 6992370 | Memory cell structure having nitride layer with reduced charge loss and method for fabricating same | George Jonathan Kluth, Robert Clark-Phelps, Joong S. Jeon, Huicai Zhong, Arvind Halliyal +3 more | 2006-01-31 |
| 6989320 | Bitline implant utilizing dual poly | Weidong Qian, Jean Y. Yang, Sameer Haddad | 2006-01-24 |