Issued Patents All Time
Showing 76–100 of 159 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6735123 | High density dual bit flash memory cell with non planar structure | Nicholas H. Tripsas, Wei Zheng, Effiong Ibok, Fred Cheung | 2004-05-11 |
| 6730564 | Salicided gate for virtual ground arrays | Yu Sun, Chi Chang, Hidehiko Shiraiwa | 2004-05-04 |
| 6727143 | Method and system for reducing charge gain and charge loss when using an ARC layer in interlayer dielectric formation | Angela T. Hui, Yu Sun, David Matsumoto | 2004-04-27 |
| 6720133 | Memory manufacturing process using disposable ARC for wordline formation | Kouros Ghandehari, Tazrien Kamal, Jean Y. Yang, Emmanuil H. Lingunis, Hidehiko Shiraiwa | 2004-04-13 |
| 6707078 | Dummy wordline for erase and bitline leakage | Hidehiko Shiraiwa, Yider Wu, Jean Y. Yang, Darlene Hamilton | 2004-03-16 |
| 6706595 | Hard mask process for memory device without bitline shorts | Jean Y. Yang, Hidehiko Shiraiwa, Yider Wu, Emmanuil Lingunis, Tazrien Kamal | 2004-03-16 |
| 6680509 | Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory | Yider Wu, Jean Y. Yang, Emmanuel H. Lingunis, Yu Sun | 2004-01-20 |
| 6674138 | Use of high-k dielectric materials in modified ONO structure for semiconductor devices | Arvind Halliyal, Kuo-Tung Chang, Nicholas H. Tripsas, Robert B. Ogle | 2004-01-06 |
| 6670241 | Semiconductor memory with deuterated materials | Tazrien Kamal, Arvind Halliyal, Minh Van Ngo, Jean Y. Yang, Hidehiko Shiraiwa +1 more | 2003-12-30 |
| 6667243 | Etch damage repair with thermal annealing | Nicholas H. Tripsas, Arvind Halliyal, Jeffrey A. Shields, Yider Wu | 2003-12-23 |
| 6653191 | Memory manufacturing process using bitline rapid thermal anneal | Jean Y. Yang, Arvind Halliyal, Amir H. Jafarpour, Tazrien Kamal, Emmanuil Lingunis +1 more | 2003-11-25 |
| 6653190 | Flash memory with controlled wordline width | Jean Y. Yang, Kouros Ghandehari, Tazrien Kamal, Minh Van Ngo, Dawn Hopper +2 more | 2003-11-25 |
| 6645801 | Salicided gate for virtual ground arrays | Yu Sun, Chi Chang | 2003-11-11 |
| 6642573 | Use of high-K dielectric material in modified ONO structure for semiconductor devices | Arvind Halliyal, Wei Zhang, Mark Randolph, Fred Cheung | 2003-11-04 |
| 6639271 | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same | Wei Zheng, Mark Randolph, Nicholas H. Tripsas, Zoran Krivokapic, Jack F. Thomas | 2003-10-28 |
| 6635943 | Method and system for reducing charge gain and charge loss in interlayer dielectric formation | Angela T. Hui, Tuan Pham, Richard J. Huang, Lu You | 2003-10-21 |
| 6630383 | Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer | Effiong Ibok, Wei Zheng, Nicholas H. Tripsas, Fred Cheung | 2003-10-07 |
| 6630384 | Method of fabricating double densed core gates in sonos flash memory | Yu Sun, Michael A. Van Buskirk | 2003-10-07 |
| 6627945 | Memory device and method of making | Nicholas H. Tripsas | 2003-09-30 |
| 6620717 | Memory with disposable ARC for wordline formation | Tazrien Kamal, Scott A. Bell, Kouros Ghandehari, Jeffrey A. Shields, Jean Y. Yang | 2003-09-16 |
| 6617215 | Memory wordline hard mask | Arvind Halliyal, Tazrien Kamal, Minh Van Ngo, Jeffrey A. Shields, Jean Y. Yang +3 more | 2003-09-09 |
| 6605511 | Method of forming nitridated tunnel oxide barriers for flash memory technology circuitry and STI and LOCOS isolation | Tuan Pham, Yu Sun, Chi Chang | 2003-08-12 |
| 6589841 | Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate | Tuan Pham, Sameer Haddad, Angela T. Hui | 2003-07-08 |
| 6579778 | Source bus formation for a flash memory using silicide | Nicholas H. Tripsas | 2003-06-17 |
| 6573151 | Method of forming zero marks | Terence Tong | 2003-06-03 |