Issued Patents All Time
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8729549 | Test structure and methodology for three-dimensional semiconductor structures | Kerry Bernstein, Jerome L. Cann, Christopher McCall Durham, Paul D. Kartschoke, Peter Juergen Klim | 2014-05-20 |
| 8423847 | Microcontroller for logic built-in self test (LBIST) | Gary D. Grise, David E. Lackey, Steven F. Oakland | 2013-04-16 |
| 8294149 | Test structure and methodology for three-dimensional semiconductor structures | Kerry Bernstein, Jerome L. Cann, Christopher McCall Durham, Paul D. Kartschoke, Peter Juergen Klim | 2012-10-23 |
| 8205124 | Microcontroller for logic built-in self test (LBIST) | Gary D. Grise, David E. Lackey, Steven F. Oakland | 2012-06-19 |
| 7916826 | Diagnostic method and apparatus for non-destructively observing latch data | Darren L. Anand, John R. Goss, Peter O. Jakobsen, Michael R. Ouellette, Thomas O. Sopchak | 2011-03-29 |
| 7870454 | Structure for system for and method of performing high speed memory diagnostics via built-in-self-test | Kevin W. Gorman, Emory D. Keller, Michael R. Ouellette | 2011-01-11 |
| 7607060 | System and method for performing high speed memory diagnostics via built-in-self-test | Kevin W. Gorman, Emory D. Keller, Michael R. Ouellette | 2009-10-20 |
| 7490280 | Microcontroller for logic built-in self test (LBIST) | Gary D. Grise, David E. Lackey, Steven F. Oakland | 2009-02-10 |
| 7453973 | Diagnostic method and apparatus for non-destructively observing latch data | Darren L. Anand, John R. Goss, Peter O. Jacobsen, Michael R. Ouellette, Thomas G. Sopchak | 2008-11-18 |
| 7435990 | Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer | Brion Keller, Bernd Koenemann, David E. Lackey | 2008-10-14 |
| 7381986 | Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer | Brion Keller, Bernd K. F. Koenermann, David E. Lackey | 2008-06-03 |
| 7237165 | Method for testing embedded DRAM arrays | Laura S. Chadwick, William R. J. Corbin, Jeffrey H. Dreibelbis, Erik A. Nelson, Thomas E. Obremski +1 more | 2007-06-26 |
| 7145977 | Diagnostic method and apparatus for non-destructively observing latch data | Darren L. Anand, John R. Goss, Peter O. Jakobsen, Michael R. Ouellette, Thomas G. Sopchak | 2006-12-05 |
| 7103814 | Testing logic and embedded memory in parallel | William R. J. Corbin, Brian R. Kessler, Erik A. Nelson, Thomas E. Obremski | 2006-09-05 |
| 7103816 | Method and system for reducing test data volume in the testing of logic products | Frank Distler, Leonard O. Farnsworth, III, Andrew Ferko, Brion Keller, Bernd Koenemann | 2006-09-05 |
| 7073100 | Method for testing embedded DRAM arrays | Laura S. Chadwick, William R. J. Corbin, Jeffrey H. Dreibelbis, Erik A. Nelson, Thomas E. Obremski +1 more | 2006-07-04 |
| 6931346 | Method and apparatus for reduced pin count package connection verification | Michael Combs | 2005-08-16 |
| 6804803 | Method for testing integrated logic circuits | Carl Barnhart, Robert W. Bassett, Brion Keller, David E. Lackey, Mark R. Taylor | 2004-10-12 |
| 6768694 | Method of electrically blowing fuses under control of an on-chip tester interface apparatus | Darren L. Anand, Bruce Cowan, L. Farnsworth, Pamela S. Gillis, Peter O. Jakobsen +3 more | 2004-07-27 |
| 6754864 | System and method to predetermine a bitmap of a self-tested embedded array | David Gangl, Matthew S. Grady, David Iverson, Gary W. Maier, Robert Edward Shearer | 2004-06-22 |
| 6730529 | Method for chip testing | Howard L. Kalter, H. Bernhard Pogge, George S. Prokop | 2004-05-04 |
| 6724210 | Method and apparatus for reduced pin count package connection verification | Michael Combs | 2004-04-20 |
| 6708305 | Deterministic random LBIST | L. Farnsworth, Brion Keller, Bernd Koenemann, Timothy J. Koprowski, Thomas J. Snethen | 2004-03-16 |
| 6618682 | Method for test optimization using historical and actual fabrication test data | Raymond J. Bulaga, Anne Elizabeth Gattiker, John L. Harris, Phillip J. Nigh, Leo A. Noel +2 more | 2003-09-09 |
| 6549150 | Integrated test structure and method for verification of microelectronic devices | Raymond J. Bulaga, John K. Masi, Patrick Miller, Mark S. Styduhar | 2003-04-15 |