Issued Patents All Time
Showing 126–150 of 1,139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12057371 | Semiconductor device with early buried power rail (BPR) and backside power distribution network (BSPDN) | Balasubramanian Pranatharthiharan, Mukta G. Farooq, Brent A. Anderson | 2024-08-06 |
| 12046643 | Semiconductor structures with power rail disposed under active gate | Julien Frougier, Kangguo Cheng, Chanro Park | 2024-07-23 |
| 12027224 | Authenticity and yield by reading defective cells | Julien Frougier, Kangguo Cheng | 2024-07-02 |
| 12016251 | Spin-orbit torque and spin-transfer torque magnetoresistive random-access memory stack | Heng Wu, Alexander Reznicek, Bahman Hekmatshoartabari | 2024-06-18 |
| 12009435 | Integrated nanosheet field effect transistors and floating gate memory cells | Julien Frougier, Veeraraghavan S. Basker, Alexander Reznicek | 2024-06-11 |
| 12009395 | Self-aligned block for vertical FETs | Junli Wang, Choonghyun Lee, Alexander Reznicek | 2024-06-11 |
| 12002874 | Buried power rail contact | Junli Wang, Brent A. Anderson, Chen Zhang, Heng Wu | 2024-06-04 |
| 12002869 | Gate contact structures and cross-coupled contact structures for transistor devices | Youngtag Woo, Daniel Chanemougame, Bipul C. Paul, Lars Liebmann, Heimanu Niebojewski +3 more | 2024-06-04 |
| 12002856 | Vertical field effect transistor with crosslink fin arrangement | Indira Seshadri, Chen Zhang, Ekmini Anuja De Silva | 2024-06-04 |
| 12002850 | Nanosheet-based semiconductor structure with dielectric pillar | Kangguo Cheng, Julien Frougier, Chanro Park | 2024-06-04 |
| 12002808 | Dual dielectric pillar fork sheet device | Julien Frougier, Kangguo Cheng, Dimitri Houssameddine | 2024-06-04 |
| 12002805 | Local vertical interconnects for monolithic stack transistors | Heng Wu, Chen Zhang, Eric R. Miller | 2024-06-04 |
| 12002758 | Backside metal-insulator-metal (MIM) capacitors extending through backside interlayer dielectric (BILD) layer or semiconductor layer and partly through dielectric layer | Takeshi Nogami, Roy R. Yu, Balasubramanian Pranatharthiharan, Chih-Chao Yang | 2024-06-04 |
| 12002753 | Electronic fuse with passive two-terminal phase change material and method of fabrication | Kevin W. Brew, Lan Yu, Kangguo Cheng | 2024-06-04 |
| 11990508 | Dual step etch-back inner spacer formation | Andrew M. Greene, Yao Yao, Veeraraghavan S. Basker | 2024-05-21 |
| 11990412 | Buried power rails located in a base layer including first, second, and third etch stop layers | Stuart A. Sieg, Somnath Ghosh, Kisik Choi, Rishikesh Krishnan, Alexander Reznicek | 2024-05-21 |
| 11984401 | Stacked FET integration with BSPDN | Junli Wang, Mukta G. Farooq, Dechao Guo | 2024-05-14 |
| 11978796 | Contact and isolation in monolithically stacked VTFET | Chen Zhang, Lan Yu, Kangguo Cheng | 2024-05-07 |
| 11973125 | Self-aligned uniform bottom spacers for VTFETS | Hemanth Jagannathan, Jay William Strane, Eric R. Miller | 2024-04-30 |
| 11963469 | Phase change memory cell with an airgap to allow for the expansion and restriction of the PCM material | Kangguo Cheng, Carl Radens, Juntao Li | 2024-04-16 |
| 11963456 | MRAM memory array yield improvement | Dimitri Houssameddine, Kangguo Cheng, Julien Frougier | 2024-04-16 |
| 11961544 | Spin-orbit torque (SOT) magnetoresistive random-access memory (MRAM) with low resistivity spin hall effect (SHE) write line | Julien Frougier, Dimitri Houssameddine, Kangguo Cheng | 2024-04-16 |
| 11955526 | Thick gate oxide device option for nanosheet device | Kangguo Cheng, Julien Frougier, Chanro Park, Veeraraghavan S. Basker | 2024-04-09 |
| 11955369 | Recessed local interconnect formed over self-aligned double diffusion break | Lan Yu, Chen Zhang, Huimei Zhou | 2024-04-09 |
| 11948944 | Optimized contact resistance for stacked FET devices | Heng Wu, Jingyun Zhang, Julien Frougier | 2024-04-02 |