Issued Patents All Time
Showing 26–50 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10692985 | Protection of high-K dielectric during reliability anneal on nanosheet structures | Nicolas Loubet, Sanjay C. Mehta, Vijay Narayanan | 2020-06-23 |
| 10680081 | Vertical transistors with improved top source/drain junctions | Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2020-06-09 |
| 10658521 | Enabling residue free gap fill between nanosheets | Indira Seshadri, Ekmini Anuja De Silva, Jing Guo, Ruqiang Bao, Nelson Felix | 2020-05-19 |
| 10629702 | Approach to bottom dielectric isolation for vertical transport fin field effect transistors | Zhenxing Bi, Thamarai S. Devarajan, Balasubramanian Pranatharthiharan, Sanjay C. Mehta | 2020-04-21 |
| 10615078 | Method to recess cobalt for gate metal application | Georges Jacobi, Vimal Kamineni, Randolph F. Knarr, Balasubramanian Pranatharthiharan | 2020-04-07 |
| 10607922 | Controlling via critical dimension during fabrication of a semiconductor wafer | Yann Mignot, Yongan Xu | 2020-03-31 |
| 10546785 | Method to recess cobalt for gate metal application | Georges Jacobi, Vimal Kamineni, Randolph F. Knarr, Balasubramanian Pranatharthiharan | 2020-01-28 |
| 10475904 | Methods of forming merged source/drain regions on integrated circuit products | Hiroaki Niimi, Steven Bentley, Romain Lallement, Brent A. Anderson, Junli Wang | 2019-11-12 |
| 10395936 | Wafer element with an adjusted print resolution assist feature | Yann Mignot | 2019-08-27 |
| 10395938 | Wafer element with an adjusted print resolution assist feature | Yann Mignot | 2019-08-27 |
| 10396208 | Vertical transistors with improved top source/drain junctions | Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2019-08-27 |
| 10374034 | Undercut control in isotropic wet etch processes | Chi-Chun Liu, Kristin Schmidt, Ekmini Anuja De Silva, Noel Arellano, Robin Hsin Kuo Chao +2 more | 2019-08-06 |
| 10304936 | Protection of high-K dielectric during reliability anneal on nanosheet structures | Nicolas Loubet, Sanjay C. Mehta, Vijay Narayanan | 2019-05-28 |
| 10256320 | Vertical field-effect-transistors having a silicon oxide layer with controlled thickness | Chi-Chun Liu, Sanjay C. Mehta, Luciana Meli, Kristin Schmidt, Ankit Vora | 2019-04-09 |
| 10256161 | Dual work function CMOS devices | Hemanth Jagannathan, Koji Watanabe | 2019-04-09 |
| 10242920 | Integrating and isolating NFET and PFET nanosheet transistors on a substrate | Michael A. Guillorn, Nicolas Loubet | 2019-03-26 |
| 10170326 | Wafer element with an adjusted print resolution assist feature | Yann Mignot | 2019-01-01 |
| 10074575 | Integrating and isolating nFET and pFET nanosheet transistors on a substrate | Michael A. Guillorn, Nicolas Loubet | 2018-09-11 |
| 10049876 | Removal of trilayer resist without damage to underlying structure | Soon-Cheon Seo, Indira Seshadri, John R. Sporre | 2018-08-14 |
| 9831100 | Solution based etching of titanium carbide and titanium nitride structures | John Foster, Sean Xuan Lin, Ruilong Xie | 2017-11-28 |
| 9496371 | Channel protection during fin fabrication | Russell H. Arndt, Hong He, Gauri Karve, Fee Li Lie | 2016-11-15 |
| 9373697 | Spacer replacement for replacement metal gate semiconductor devices | Sanjay C. Mehta, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita | 2016-06-21 |
| 9373580 | Dual hard mask lithography process | John C. Arnold, Sean D. Burns, Steven J. Holmes, David V. Horak, Yunpeng Yin | 2016-06-21 |
| 9287130 | Method for single fin cuts using selective ion implants | Xiuyu Cai, Ajey Poovannummoottil Jacob, Ruilong Xie, Bruce B. Doris, Kangguo Cheng +7 more | 2016-03-15 |
| 9171927 | Spacer replacement for replacement metal gate semiconductor devices | Sanjay C. Mehta, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita | 2015-10-27 |