Issued Patents 2022
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11532584 | Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling | Robert Alan May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Javier Soto Gonzalez, Kwangmo Chris Lim +1 more | 2022-12-20 |
| 11521931 | Microelectronic structures including bridges | Jason M. Gamba, Nitin A. Deshpande, Mohit Bhatia, Omkar G. Karhade, Bai Nie +2 more | 2022-12-06 |
| 11508662 | Device and method of very high density routing used with embedded multi-die interconnect bridge | Robert Alan May, Wei-Lun Kane Jen, Jonathan L. Rosch, Islam A. Salama | 2022-11-22 |
| 11495552 | Substrate integrated thin film capacitors using amorphous high-k dielectrics | Aleksandar Aleksov, Thomas L. Sounart, Henning Braunisch, Prithwish Chatterjee, Andrew J. Brown | 2022-11-08 |
| 11443885 | Thin film barrier seed metallization in magnetic-plugged through hole inductor | Srinivas V. Pietambaram, Sandeep Gaan, Sri Ranga Sai Boyapati, Prithwish Chatterjee, Sameer Paital +2 more | 2022-09-13 |
| 11430740 | Microelectronic device with embedded die substrate on interposer | Robert Alan May, Islam A. Salama, Sri Ranga Sai Boyapati, Sheng Li, Robert L. Sankman +1 more | 2022-08-30 |
| 11404389 | In-situ component fabrication of a highly efficient, high inductance air core inductor integrated into substrate packages | Jeremy Ecton, Suddhasattwa Nad, Yonggang Li, Xiaoying Guo | 2022-08-02 |
| 11393766 | Multi-chip package with high density interconnects | Aleksandar Aleksov, Adel A. Elsherbini, Robert Alan May, Sri Ranga Sai Boyapati | 2022-07-19 |
| 11380472 | High-permeability magnetic-dielectric film-based inductors | Srinivas V. Pietambaram, Rahul N. Manepalli | 2022-07-05 |
| 11348718 | Substrate embedded magnetic core inductors and method of making | Srinivas V. Pietambaram, Gang Duan, Yonggang Li, Sameer Paital | 2022-05-31 |
| 11322444 | Lithographic cavity formation to enable EMIB bump pitch scaling | Hiroki Tanaka, Robert Alan May, Sameer Paital, Bai Nie, Jesse C. Jones +1 more | 2022-05-03 |
| 11309239 | Electromigration resistant and profile consistent contact arrays | Srinivas V. Pietambaram, Jung Kyu Han, Ali Lehaf, Steve Cho, Thomas HEATON +3 more | 2022-04-19 |
| 11309192 | Integrated circuit package supports | Robert Alan May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov | 2022-04-19 |
| 11272619 | Apparatus with embedded fine line space in a cavity, and a method for forming the same | Robert Alan May, Yikang Deng, Ji-Yong Park, Maroun D. Moussallem, Amruthavalli Pallavi Alur +2 more | 2022-03-08 |
| 11264239 | Polarization defined zero misalignment vias for semiconductor packaging | Hiroki Tanaka, Aleksandar Aleksov, Sri Ranga Sai Boyapati, Robert Alan May | 2022-03-01 |
| 11264346 | Sacrificial dielectric for lithographic via formation to enable via scaling in high density interconnect packaging | Sri Ranga Sai Boyapati, Hiroki Tanaka, Robert Alan May | 2022-03-01 |
| 11264307 | Dual-damascene zero-misalignment-via process for semiconductor packaging | Aleksandar Aleksov, Hiroki Tanaka, Robert Alan May, Changhua Liu, Chung Kwang Christopher Tan +2 more | 2022-03-01 |
| 11257745 | Electroless metal-defined thin pad first level interconnects for lithographically defined vias | Aleksandar Aleksov, Veronica Strong, Arnab Sarkar | 2022-02-22 |
| 11244912 | Semiconductor package having a coaxial first layer interconnect | Sai Vadlamani, Aleksandar Aleksov, Rahul Jain, Kyu Oh Lee, Robert Alan May +2 more | 2022-02-08 |
| 11227849 | Electroless-catalyst doped-mold materials for integrated-circuit die packaging architectures | Brandon C. Marin, Srinivas V. Pietambaram, Gang Duan, Sameer Paital | 2022-01-18 |