Issued Patents 2022
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11532584 | Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling | Robert Alan May, Kristof Darmawikarta, Srinivas V. Pietambaram, Javier Soto Gonzalez, Kwangmo Chris Lim +1 more | 2022-12-20 |
| 11488918 | Surface finishes with low rBTV for fine and mixed bump pitch architectures | Kristof Darmawaikarta, Robert Alan May, Sashi S. Kandanur, Srinivas V. Pietambaram, Steve Cho +7 more | 2022-11-01 |
| 11443885 | Thin film barrier seed metallization in magnetic-plugged through hole inductor | Kristof Darmawikarta, Srinivas V. Pietambaram, Sandeep Gaan, Prithwish Chatterjee, Sameer Paital +2 more | 2022-09-13 |
| 11430740 | Microelectronic device with embedded die substrate on interposer | Robert Alan May, Islam A. Salama, Sheng Li, Kristof Darmawikarta, Robert L. Sankman +1 more | 2022-08-30 |
| 11393766 | Multi-chip package with high density interconnects | Aleksandar Aleksov, Adel A. Elsherbini, Kristof Darmawikarta, Robert Alan May | 2022-07-19 |
| 11309192 | Integrated circuit package supports | Kristof Darmawikarta, Robert Alan May, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov | 2022-04-19 |
| 11309239 | Electromigration resistant and profile consistent contact arrays | Srinivas V. Pietambaram, Jung Kyu Han, Ali Lehaf, Steve Cho, Thomas HEATON +3 more | 2022-04-19 |
| 11272619 | Apparatus with embedded fine line space in a cavity, and a method for forming the same | Kristof Darmawikarta, Robert Alan May, Yikang Deng, Ji-Yong Park, Maroun D. Moussallem +2 more | 2022-03-08 |
| 11270959 | Enabling magnetic films in inductors integrated into semiconductor packages | Kirstof Darmawikarta, Srinivas V. Pietambaram, Prithwish Chatterjee, Wei-Lun Kane Jen | 2022-03-08 |
| 11264239 | Polarization defined zero misalignment vias for semiconductor packaging | Hiroki Tanaka, Aleksandar Aleksov, Robert Alan May, Kristof Darmawikarta | 2022-03-01 |
| 11264346 | Sacrificial dielectric for lithographic via formation to enable via scaling in high density interconnect packaging | Kristof Darmawikarta, Hiroki Tanaka, Robert Alan May | 2022-03-01 |
| 11264307 | Dual-damascene zero-misalignment-via process for semiconductor packaging | Aleksandar Aleksov, Hiroki Tanaka, Robert Alan May, Kristof Darmawikarta, Changhua Liu +2 more | 2022-03-01 |
| 11244912 | Semiconductor package having a coaxial first layer interconnect | Sai Vadlamani, Aleksandar Aleksov, Rahul Jain, Kyu Oh Lee, Kristof Darmawikarta +2 more | 2022-02-08 |