RM

Robert Alan May

IN Intel: 17 patents #80 of 4,681Top 2%
Overall (2022): #2,717 of 548,613Top 1%
17
Patents 2022

Issued Patents 2022

Patent #TitleCo-InventorsDate
11532584 Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling Sri Ranga Sai Boyapati, Kristof Darmawikarta, Srinivas V. Pietambaram, Javier Soto Gonzalez, Kwangmo Chris Lim +1 more 2022-12-20
11508662 Device and method of very high density routing used with embedded multi-die interconnect bridge Wei-Lun Kane Jen, Jonathan L. Rosch, Islam A. Salama, Kristof Darmawikarta 2022-11-22
11488918 Surface finishes with low rBTV for fine and mixed bump pitch architectures Kristof Darmawaikarta, Sashi S. Kandanur, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Steve Cho +7 more 2022-11-01
11430740 Microelectronic device with embedded die substrate on interposer Islam A. Salama, Sri Ranga Sai Boyapati, Sheng Li, Kristof Darmawikarta, Robert L. Sankman +1 more 2022-08-30
11393766 Multi-chip package with high density interconnects Aleksandar Aleksov, Adel A. Elsherbini, Kristof Darmawikarta, Sri Ranga Sai Boyapati 2022-07-19
11373951 Via structures having tapered profiles for embedded interconnect bridge substrates Jeremy Ecton, Hiroki Tanaka, Oscar Ojeda, Arnab Roy, Vahidreza Parichehreh +2 more 2022-06-28
11322444 Lithographic cavity formation to enable EMIB bump pitch scaling Kristof Darmawikarta, Hiroki Tanaka, Sameer Paital, Bai Nie, Jesse C. Jones +1 more 2022-05-03
11309192 Integrated circuit package supports Kristof Darmawikarta, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov 2022-04-19
11309239 Electromigration resistant and profile consistent contact arrays Srinivas V. Pietambaram, Jung Kyu Han, Ali Lehaf, Steve Cho, Thomas HEATON +3 more 2022-04-19
11302643 Microelectronic component having molded regions with through-mold vias Sanka Ganesan, Ram Viswanath, Xavier Francois Brun, Tarek A. Ibrahim, Jason M. Gamba +1 more 2022-04-12
11272619 Apparatus with embedded fine line space in a cavity, and a method for forming the same Kristof Darmawikarta, Yikang Deng, Ji-Yong Park, Maroun D. Moussallem, Amruthavalli Pallavi Alur +2 more 2022-03-08
11264346 Sacrificial dielectric for lithographic via formation to enable via scaling in high density interconnect packaging Kristof Darmawikarta, Sri Ranga Sai Boyapati, Hiroki Tanaka 2022-03-01
11264307 Dual-damascene zero-misalignment-via process for semiconductor packaging Aleksandar Aleksov, Hiroki Tanaka, Kristof Darmawikarta, Changhua Liu, Chung Kwang Christopher Tan +2 more 2022-03-01
11264239 Polarization defined zero misalignment vias for semiconductor packaging Hiroki Tanaka, Aleksandar Aleksov, Sri Ranga Sai Boyapati, Kristof Darmawikarta 2022-03-01
11251113 Methods of embedding magnetic structures in substrates Sai Vadlamani, Prithwish Chatterjee, Rahul Jain, Lauren A. Link, Andrew J. Brown +2 more 2022-02-15
11244912 Semiconductor package having a coaxial first layer interconnect Sai Vadlamani, Aleksandar Aleksov, Rahul Jain, Kyu Oh Lee, Kristof Darmawikarta +2 more 2022-02-08
11233009 Embedded multi-die interconnect bridge having a molded region with through-mold vias Praneeth Akkinepally, Frank Truong, Jason M. Gamba 2022-01-25