Issued Patents All Time
Showing 251–275 of 365 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8264086 | Via structure with improved reliability | Cheng-Lin Huang, Ching-Hua Hsieh | 2012-09-11 |
| 8252682 | Method for thinning a wafer | Ku-Feng Yang, Weng-Jin Wu, Hsin-Hsien Lu, Chia-Lin Yu, Chu-Sung Shih +1 more | 2012-08-28 |
| 8252665 | Protection layer for adhesive material at wafer edge | Wen-Chih Chiou, Weng-Jin Wu | 2012-08-28 |
| 8236579 | Methods and systems for lithography alignment | Hsiao-Tzu Lu, Hung-Chang Hsieh, Kuei-Shun Chen, Hsueh-Hung Fu, Ching-Hua Hsieh | 2012-08-07 |
| 8202799 | Methods of manufacturing metal-silicide features | Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chaing-Ming Chuang | 2012-06-19 |
| 8178437 | Barrier material and process for Cu interconnect | Chung-Liang Chang, Ching-Hua Hsieh | 2012-05-15 |
| 8106512 | Low resistance high reliability contact via and metal line structure for semiconductor device | Hsiang-Huan Lee, Ming-Han Lee, Ming-Shih Yeh, Chen-Hua Yu | 2012-01-31 |
| 8101489 | Approach to reduce the contact resistance | Ting-Chu Ko | 2012-01-24 |
| 8053357 | Prevention of post CMP defects in CU/FSG process | Chung-Shi Liu | 2011-11-08 |
| 7988843 | Method and apparatus for electrochemical plating semiconductor wafers | Chung-Liang Chang | 2011-08-02 |
| 7888719 | Semiconductor memory structures | Chao-An Jong | 2011-02-15 |
| 7883991 | Temporary carrier bonding and detaching processes | Wen-Jin Wu, Wen-Chih Chiou | 2011-02-08 |
| 7781316 | Methods of manufacturing metal-silicide features | Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang | 2010-08-24 |
| 7777344 | Transitional interface between metal and dielectric in interconnect structures | Chien-Hsueh Shih | 2010-08-17 |
| 7704368 | Method and apparatus for electrochemical plating semiconductor wafers | Chung-Liang Chang | 2010-04-27 |
| 7700479 | Cleaning processes in the formation of integrated circuit interconnect structures | Cheng-Lin Huang, Ching-Hua Hsieh | 2010-04-20 |
| 7682963 | Air gap for interconnect application | Hai-Ching Chen, Sunil Kumar Singh, Tien-I Bao, Chen-Hua Yu | 2010-03-23 |
| 7659198 | In-situ deposition for Cu hillock suppression | Chung-Hsien Chen, Chun-Chieh Lin, Minghsing Tsai | 2010-02-09 |
| 7625801 | Silicide formation with a pre-amorphous implant | Chii-Ming Wu, Cheng-Tung Lin, Chih-Wei Chang | 2009-12-01 |
| 7612451 | Reducing resistivity in interconnect structures by forming an inter-layer | Chih-Chao Shih, Cheng-Lin Huang, Ching-Hua Hsieh | 2009-11-03 |
| 7538434 | Copper interconnection with conductive polymer layer and method of forming the same | Chien-Hsueh Shih, Minghsing Tsai, Hung-Wen Su | 2009-05-26 |
| 7514348 | Sidewall coverage for copper damascene filling | Mei-Yun Wang, Chen-Hua Yu | 2009-04-07 |
| 7501333 | Work function adjustment on fully silicided (FUSI) gate | Wei-Jung Lin, Cheng-Tung Lin, Chih-Wei Chang | 2009-03-10 |
| 7446042 | Method for silicide formation on semiconductor devices | Chii-Ming Wu, Shih-Wei Chou, Gin Jei Wang, Cheng-Tung Lin, Chih-Wei Chang | 2008-11-04 |
| 7443029 | Adhesion of copper and etch stop layer for copper alloy | Jing-Cheng Lin, Ching-Hua Hsieh, Mong-Song Liang | 2008-10-28 |