Issued Patents All Time
Showing 25 most recent of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11838000 | Comparator integration time stabilization technique utilizing common mode mitigation scheme | Todd M. Rasmus | 2023-12-05 |
| 11764733 | C-PHY receiver with self-regulated common mode servo loop | Todd M. Rasmus, Ying Duan, Abhay Dixit | 2023-09-19 |
| 11641294 | C-PHY half-rate wire state encoder and decoder | Chulkyu Lee, Ying Duan | 2023-05-02 |
| 11585004 | Composition for cobalt or cobalt alloy electroplating | Marco Arnold, Chiao Wei, Tzu-Tsang Huang, Shih-Ming Lin, Cheng-Chen Kuo +1 more | 2023-02-21 |
| 11528995 | Balancing pressure bearing apparatus | — | 2022-12-20 |
| 11411711 | Small loop delay clock and data recovery block for high-speed next generation C-PHY | Ying Duan, Jing Wu | 2022-08-09 |
| 11327914 | C-PHY data-triggered edge generation with intrinsic half-rate operation | Da Ying, Ying Duan, Abhay Dixit | 2022-05-10 |
| 11240077 | C-PHY half-rate wire state encoder and decoder | Chulkyu Lee, Ying Duan | 2022-02-01 |
| 11116319 | Seat | Yun-Cheng Hsiao | 2021-09-14 |
| 11106610 | Seperation of low-power and high-speed analog front-end receivers | Ying Duan, Mansoor Basha Shaik, Harry Huy Dang, Abhay Dixit | 2021-08-31 |
| 11095425 | Small loop delay clock and data recovery block for high-speed next generation C-PHY | Ying Duan, Jing Wu | 2021-08-17 |
| 11038666 | Open-loop, super fast, half-rate clock and data recovery for next generation C-PHY interfaces | Ying Duan, Abhay Dixit | 2021-06-15 |
| 11023409 | MIPI D-PHY receiver auto rate detection and high-speed settle time control | Yasser Ahmed, Ying Duan | 2021-06-01 |
| 10833899 | Low power physical layer driver topologies | Chulkyu Lee, Dhaval Sejpal | 2020-11-10 |
| 10615785 | Fully compensated complementary duty cycle correction circuits | Ying Duan, Abhay Dixit, Harry Huy Dang, Thomas Clark Bryan | 2020-04-07 |
| 10419252 | Low power physical layer driver topologies | Chulkyu Lee, Dhaval Sejpal | 2019-09-17 |
| 10419246 | C-PHY training pattern for adaptive equalization, adaptive edge tracking and delay calibration | Ying Duan, Abhay Dixit, Jing Wu, Harry Huy Dang | 2019-09-17 |
| 10389315 | Three-input continuous-time amplifier and equalizer for multi-level signaling | Chulkyu Lee, Ying Duan | 2019-08-20 |
| 10333690 | Calibration pattern and duty-cycle distortion correction for clock data recovery in a multi-wire, multi-phase interface | Ying Duan, Abhay Dixit, Chulkyu Lee | 2019-06-25 |
| 10298381 | Multiphase clock data recovery with adaptive tracking for a multi-wire, multi-phase interface | Chulkyu Lee, Ying Duan | 2019-05-21 |
| 10289600 | Reducing transmitter encoding jitter in a C-PHY interface using multiple clock phases to launch symbols | Dhaval Sejpal, Chulkyu Lee, Ohjoon Kwon, George Alan Wiley | 2019-05-14 |
| 9998154 | Low power physical layer driver topologies | Chulkyu Lee, Dhaval Sejpal | 2018-06-12 |
| 9978681 | Semiconductor device | Hung-Wen Su, Ming-Hsing Tsai | 2018-05-22 |
| 9819523 | Intelligent equalization for a three-transmitter multi-phase system | Chulkyu Lee, George Alan Wiley | 2017-11-14 |
| 9496879 | Multiphase clock data recovery for a 3-phase interface | Ying Duan, Chulkyu Lee, Harry Huy Dang, Ohjoon Kwon | 2016-11-15 |