Issued Patents All Time
Showing 201–225 of 365 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9466525 | Interconnect structures comprising flexible buffer layers | Chao-Hsien Peng, Hsin-Yen Huang, Hsiang-Huan Lee | 2016-10-11 |
| 9449875 | Wafer backside interconnect structure connected to TSVs | Ming-Fa Chen, Wen-Chih Chiou | 2016-09-20 |
| 9437540 | Additional etching to increase via contact area | Pei-Yi Lin, Chung-Ju Lee | 2016-09-06 |
| 9431297 | Method of forming an interconnect structure for a semiconductor device | Yung-Hsu Wu, Cheng-Hsiung Tsai, Yu-Sheng Chang, Chia-Tien Wu, Chung-Ju Lee +4 more | 2016-08-30 |
| 9418868 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu +4 more | 2016-08-16 |
| 9412649 | Method of fabricating semiconductor device | Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu +4 more | 2016-08-09 |
| 9385029 | Method for forming recess-free interconnect structure | Chao-Hsien Peng, Hsiang-Huan Lee | 2016-07-05 |
| 9384994 | Method of forming multiple patterning spacer structures | Chih Wei Lu, Chung-Ju Lee | 2016-07-05 |
| 9343400 | Dual damascene gap filling process | Hsiang-Huan Lee | 2016-05-17 |
| 9330989 | System and method for chemical-mechanical planarization of a metal layer | Yung-Hsu Wu, Shih-Kang Fu, Hsin-Chieh Yao, Hsiang-Huan Lee, Chung-Ju Lee +1 more | 2016-05-03 |
| 9318439 | Interconnect structure and manufacturing method thereof | Shin-Yi Yang, Hsi-Wen Tien, Ming-Han Lee, Hsiang-Huan Lee | 2016-04-19 |
| 9318364 | Semiconductor device metallization systems and methods | Hsiang-Huan Lee, Keith Kuang-Kuo Koai, Hai-Ching Chen, Tung-Ching Tseng, Wen-Cheng Yang +3 more | 2016-04-19 |
| 9305837 | Semiconductor arrangement and formation thereof | Chia-Tien Wu, Tien-Lu Lin | 2016-04-05 |
| 9293413 | Semiconductor devices and methods of manufacture thereof | Hsin-Chieh Yao, Chung-Ju Lee, Tien-I Bao | 2016-03-22 |
| 9269668 | Interconnect having air gaps and polymer wrapped conductive lines | Shin-Yi Yang, Hsiang-Huan Lee, Ming-Han Lee, Hsi-Wen Tien | 2016-02-23 |
| 9252049 | Method for forming interconnect structure that avoids via recess | Chao-Hsien Peng, Tsung-Min Huang, Hsiang-Huan Lee | 2016-02-02 |
| 9230911 | Interconnect structure and method of forming the same | Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Tien-I Bao | 2016-01-05 |
| 9224643 | Structure and method for tunable interconnect scheme | Chung-Ju Lee, Tien-I Bao, Ming-Shih Yeh, Hai-Ching Chen | 2015-12-29 |
| 9219033 | Via pre-fill on back-end-of-the-line interconnect layer | Chao-Hsien Peng, Chi-Liang Kuo, Ming-Han Lee, Hsiang-Huan Lee | 2015-12-22 |
| 9209076 | Method of double patterning lithography process using plurality of mandrels for integrated circuit applications | Hsin-Chieh Yao, Chung-Ju Lee, Yung-Hsu Wu, Tien-I Bao | 2015-12-08 |
| 9177797 | Lithography using high selectivity spacers for pitch reduction | Yu-Sheng Chang, Chung-Ju Lee, Cheng-Hsiung Tsai, Yung-Hsu Wu, Hsiang-Huan Lee +5 more | 2015-11-03 |
| 9159579 | Lithography using multilayer spacer for reduced spacer footing | Chao-Hsien Peng, Hsiang-Huan Lee | 2015-10-13 |
| 9153478 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Shih-Ming Chang, Ken-Hsien Hsieh, Ming-Feng Shieh, Chih-Ming Lai +6 more | 2015-10-06 |
| 9142509 | Copper interconnect structure and method for forming the same | Chen-Hua Yu, Hsiang-Huan Lee, Ching-Fu Yeh | 2015-09-22 |
| 9136106 | Method for integrated circuit patterning | Chieh-Han Wu, Chung-Ju Lee, Cheng-Hsiung Tsai, Ming-Feng Shieh, Ru-Gun Liu +1 more | 2015-09-15 |