Issued Patents All Time
Showing 151–175 of 365 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10312139 | Interconnect structure having an etch stop layer over conductive lines | Cheng-Hsiung Tsai, Chung-Ju Lee, Tien-I Bao | 2019-06-04 |
| 10269915 | Vertical MOS transistor and fabricating method thereof | Tai-I Yang, Yung-Chih Wang, Shin-Yi Yang, Chih Wei Lu, Hsin-Ping Chen | 2019-04-23 |
| 10269706 | Semiconductor device and manufacturing method thereof | Ming-Han Lee | 2019-04-23 |
| 10269634 | Semiconductor device having voids and method of forming same | Yung-Hsu Wu, Chien-Hua Huang, Chung-Ju Lee, Tien-I Bao | 2019-04-23 |
| 10170306 | Method of double patterning lithography process using plurality of mandrels for integrated circuit applications | Chung-Ju Lee, Hsin-Chieh Yao, Tien-I Bao, Yung-Hsu Wu | 2019-01-01 |
| 10164018 | Semiconductor interconnect structure having graphene-capped metal interconnects | Shin-Yi Yang, Ching-Fu Yeh, Ming-Han Lee | 2018-12-25 |
| 10163786 | Method of forming metal interconnection | Shin-Yi Yang, Ming-Han Lee, Tz-Jun Kuo | 2018-12-25 |
| 10163753 | Method for forming interconnect structure of semiconductor device | Ming-Han Lee | 2018-12-25 |
| 10163654 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu +4 more | 2018-12-25 |
| 10121698 | Method of manufacturing a semiconductor device | Hsiang-Huan Lee, Kuang-Kuo Koai, Hai-Ching Chen, Tung-Ching Tseng, Wen-Cheng Yang +3 more | 2018-11-06 |
| 10049919 | Semiconductor device including a target integrated circuit pattern | Chieh-Han Wu, Cheng-Hsiung Tsai, Chung-Ju Lee, Ming-Feng Shieh, Ru-Gun Liu +1 more | 2018-08-14 |
| 10014175 | Lithography using high selectivity spacers for pitch reduction | Yu-Sheng Chang, Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Hsiang-Huan Lee +5 more | 2018-07-03 |
| 10000373 | Nano-electromechanical system (NEMS) device structure and method for forming the same | Hsin-Ping Chen, Carlos H. Diaz, Ken-Ichi Goto, Tai-I Yang | 2018-06-19 |
| 9997440 | Protection layer for adhesive material at wafer edge | Wen-Chih Chiou, Weng-Jin Wu | 2018-06-12 |
| 9997404 | Method of forming an interconnect structure for a semiconductor device | Yung-Hsu Wu, Cheng-Hsiung Tsai, Yu-Sheng Chang, Chia-Tien Wu, Chung-Ju Lee +4 more | 2018-06-12 |
| 9978708 | Wafer backside interconnect structure connected to TSVs | Ming-Fa Chen, Wen-Chih Chiou | 2018-05-22 |
| 9972529 | Method of forming metal interconnection | Shin-Yi Yang, Ming-Han Lee, Tz-Jun Kuo | 2018-05-15 |
| 9922927 | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer | Yung-Hsu Wu, Hai-Ching Chen, Jung-Hsun Tsai, Tien-I Bao | 2018-03-20 |
| 9911646 | Self-aligned double spacer patterning process | Cheng-Hsiung Tsai, Yung-Hsu Wu, Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao | 2018-03-06 |
| 9911623 | Via connection to a partially filled trench | Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee +1 more | 2018-03-06 |
| 9892933 | Lithography using multilayer spacer for reduced spacer footing | Chao-Hsien Peng, Hsiang-Huan Lee | 2018-02-13 |
| 9837310 | Method of manufacturing a semiconductor device | Chao-Hsien Peng, Chi-Liang Kuo, Hsiang-Huan Lee | 2017-12-05 |
| 9831117 | Self-aligned double spacer patterning process | Yung-Hsu Wu, Tsung-Min Huang, Cheng-Hsiung Tsai, Chung-Ju Lee, Tien-I Bao | 2017-11-28 |
| 9818644 | Interconnect structure and manufacturing method thereof | Shin-Yi Yang, Hsi-Wen Tien, Ming-Han Lee, Hsiang-Huan Lee | 2017-11-14 |
| 9799558 | Method for forming conductive structure in semiconductor structure | Hsi-Wen Tien, Carlos H. Diaz, Chung-Ju Lee, Tien-I Bao | 2017-10-24 |