Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12308282 | Interconnect structure without barrier layer on bottom surface of via | Chien-Hsin Ho, Ming-Han Lee | 2025-05-20 |
| 11715689 | Method of forming metal interconnection | Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue | 2023-08-01 |
| 11551967 | Via structure and methods for forming the same | Meng-Pei Lu, Ming-Han Lee, Shin-Yi Yang | 2023-01-10 |
| 11322391 | Interconnect structure without barrier layer on bottom surface of via | Chien-Hsin Ho, Ming-Han Lee | 2022-05-03 |
| 10714424 | Method of forming metal interconnection | Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue | 2020-07-14 |
| 10453740 | Interconnect structure without barrier layer on bottom surface of via | Chien-Hsin Ho, Ming-Han Lee | 2019-10-22 |
| 10163786 | Method of forming metal interconnection | Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue | 2018-12-25 |
| 9972529 | Method of forming metal interconnection | Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue | 2018-05-15 |
| 9842767 | Method of forming an interconnection | Ming-Han Lee, Chien-Hsin Ho, Hsiang-Huan Lee | 2017-12-12 |
| 9640431 | Method for via plating with seed layer | Shin-Yi Yang, Ching-Fu Yeh, Hsiang-Huan Lee, Ming-Han Lee | 2017-05-02 |
| 9613856 | Method of forming metal interconnection | Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue | 2017-04-04 |
| 9343356 | Back end of the line (BEOL) interconnect scheme | Chi-Liang Kuo, Hsiang-Huan Lee | 2016-05-17 |
| 9324608 | Method for via plating with seed layer | Shin-Yi Yang, Ching-Fu Yeh, Hsiang-Huan Lee, Ming-Han Lee | 2016-04-26 |
| 9054163 | Method for via plating with seed layer | Shin-Yi Yang, Ching-Fu Yeh, Hsiang-Huan Lee, Ming-Han Lee | 2015-06-09 |
| 8749060 | Method of semiconductor integrated circuit fabrication | Ming-Han Lee, Chien-Hsin Ho, Hsiang-Huan Lee | 2014-06-10 |