Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412837 | Interconnect structure including topological material | Shin-Yi Yang, Cian-Yu Chen, Yun-Chi Chiang, Ming-Han Lee | 2025-09-09 |
| 12347776 | Integrated chip with graphene based interconnect | Shin-Yi Yang, Chin-Lung Chung, Ming-Han Lee, Shau-Lin Shue | 2025-07-01 |
| 12300599 | Method for forming semiconductor structure | Shin-Yi Yang, Shu-Wei Li, Chin-Lung Chung, Ming-Han Lee | 2025-05-13 |
| 12218060 | Integrated chip with graphene based interconnect | Shin-Yi Yang, Chin-Lung Chung, Ming-Han Lee, Shau-Lin Shue | 2025-02-04 |
| 12068253 | Semiconductor structure with two-dimensional conductive structures | Shu-Wei Li, Yu-Chen Chan, Shin-Yi Yang, Ming-Han Lee | 2024-08-20 |
| 12027419 | Semiconductor device including liner structure | Ching-Fu Yeh, Yu-Chen Chan, Guanyu Luo, Chao-Hsien Peng, Shin-Yi Yang +2 more | 2024-07-02 |
| 11908794 | Protection liner on interconnect wire to enlarge processing window for overlying interconnect via | Shin-Yi Yang, Hsin-Yen Huang, Ming-Han Lee, Shau-Lin Shue, Yu-Chen Chan | 2024-02-20 |
| 11682616 | Semiconductor structure and method for forming the same | Shin-Yi Yang, Shu-Wei Li, Chin-Lung Chung, Ming-Han Lee | 2023-06-20 |
| 11551967 | Via structure and methods for forming the same | Ming-Han Lee, Shin-Yi Yang, Tz-Jun Kuo | 2023-01-10 |
| 11309241 | Protection liner on interconnect wire to enlarge processing window for overlying interconnect via | Shin-Yi Yang, Hsin-Yen Huang, Ming-Han Lee, Shau-Lin Shue, Yu-Chen Chan | 2022-04-19 |
| 10879115 | Semiconductor device and forming method thereof | Ming-Han Lee, Shih-Kang Fu, Shau-Lin Shue | 2020-12-29 |