Issued Patents All Time
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12027419 | Semiconductor device including liner structure | Ching-Fu Yeh, Yu-Chen Chan, Guanyu Luo, Meng-Pei Lu, Shin-Yi Yang +2 more | 2024-07-02 |
| 11908789 | Selective formation of conductor nanowires | Hsiang-Huan Lee, Shau-Lin Shue | 2024-02-20 |
| 10930552 | Method of semiconductor integrated circuit fabrication | Ching-Fu Yeh, Hsien-Chang Wu, Hsiang-Huan Lee | 2021-02-23 |
| 10490497 | Selective formation of conductor nanowires | Hsiang-Huan Lee, Shau-Lin Shue | 2019-11-26 |
| 10453746 | Method of semiconductor integrated circuit fabrication | Ching-Fu Yeh, Hsien-Chang Wu, Hsiang-Huan Lee | 2019-10-22 |
| 9947583 | Method of semiconductor integrated circuit fabrication | Ching-Fu Yeh, Hsien-Chang Wu, Hsiang-Huan Lee | 2018-04-17 |
| 9892933 | Lithography using multilayer spacer for reduced spacer footing | Hsiang-Huan Lee, Shau-Lin Shue | 2018-02-13 |
| 9837310 | Method of manufacturing a semiconductor device | Chi-Liang Kuo, Hsiang-Huan Lee, Shau-Lin Shue | 2017-12-05 |
| 9728503 | Via pre-fill on back-end-of-the-line interconnect layer | Chi-Liang Kuo, Ming-Han Lee, Hsiang-Huan Lee, Shau-Lin Shue | 2017-08-08 |
| 9721887 | Method of forming metal interconnection | Chih Wei Lu, Ming-Han Lee, Shau-Lin Shue | 2017-08-01 |
| 9646932 | Method for forming interconnect structure that avoids via recess | Tsung-Min Huang, Hsiang-Huan Lee, Shau-Lin Shue | 2017-05-09 |
| 9570347 | Method of semiconductor integrated circuit fabrication | Ching-Fu Yeh, Hsien-Chang Wu, Hsiang-Huan Lee | 2017-02-14 |
| 9466525 | Interconnect structures comprising flexible buffer layers | Hsin-Yen Huang, Hsiang-Huan Lee, Shau-Lin Shue | 2016-10-11 |
| 9385029 | Method for forming recess-free interconnect structure | Hsiang-Huan Lee, Shau-Lin Shue | 2016-07-05 |
| 9252049 | Method for forming interconnect structure that avoids via recess | Tsung-Min Huang, Hsiang-Huan Lee, Shau-Lin Shue | 2016-02-02 |
| 9219033 | Via pre-fill on back-end-of-the-line interconnect layer | Chi-Liang Kuo, Ming-Han Lee, Hsiang-Huan Lee, Shau-Lin Shue | 2015-12-22 |
| 9159579 | Lithography using multilayer spacer for reduced spacer footing | Hsiang-Huan Lee, Shau-Lin Shue | 2015-10-13 |
| 9054161 | Method of semiconductor integrated circuit fabrication | Ching-Fu Yeh, Hsiang-Huan Lee, Hsien-Chang Wu | 2015-06-09 |
| 9030013 | Interconnect structures comprising flexible buffer layers | Hsin-Yen Huang, Hsiang-Huan Lee, Shau-Lin Shue | 2015-05-12 |
| 8916469 | Method of fabricating copper damascene | Chi-Liang Kuo, Hsiang-Huan Lee, Shau-Lin Shue | 2014-12-23 |
| 8912041 | Method for forming recess-free interconnect structure | Hsiang-Huan Lee, Shau-Lin Shue | 2014-12-16 |
| 8735280 | Method of semiconductor integrated circuit fabrication | Ching-Fu Yeh, Hsiang-Huan Lee, Hsien-Chang Wu | 2014-05-27 |
| 8034709 | Method for forming composite barrier layer | Cheng-Lin Huang, Ching-Hua Hsieh, Hsien-Ming Lee, Shing-Chyang Pan, Li-Lin Su +3 more | 2011-10-11 |
| 7453149 | Composite barrier layer | Cheng-Lin Huang, Ching-Hua Hsieh, Hsien-Ming Lee, Shing-Chyang Pan, Li-Lin Su +3 more | 2008-11-18 |
| 7405151 | Method for forming a semiconductor device | Gin Jei Wang, Chii-Ming Wu, Chih-Wei Chang, Shau-Lin Shue | 2008-07-29 |