Issued Patents All Time
Showing 101–125 of 365 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11422475 | Multi-metal fill with self-aligned patterning and dielectric with voids | Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Li-Lin Su, Yung-Hsu Wu | 2022-08-23 |
| 11404366 | Hybrid interconnect structure for self aligned via | Shin-Yi Yang, Ming-Han Lee | 2022-08-02 |
| 11387113 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu +4 more | 2022-07-12 |
| 11361994 | Fully self-aligned interconnect structure | Hsin-Ping Chen, Min Cao | 2022-06-14 |
| 11361989 | Method for manufacturing interconnect structures including air gaps | Cheng-Chin Lee, Shao-Kuan Lee, Hsin-Yen Huang, Hai-Ching Chen | 2022-06-14 |
| 11355430 | Capping layer overlying dielectric structure to increase reliability | Ting-Ya Lo, Chi-Lin Teng, Hai-Ching Chen, Hsin-Yen Huang, Shao-Kuan Lee +1 more | 2022-06-07 |
| 11355390 | Interconnect strucutre with protective etch-stop | Shao-Kuan Lee, Hai-Ching Chen, Hsin-Yen Huang, Cheng-Chin Lee | 2022-06-07 |
| 11335596 | Selective deposition for integrated circuit interconnect structures | Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hai-Ching Chen | 2022-05-17 |
| 11322395 | Dielectric capping structure overlying a conductive structure to increase stability | Hsin-Yen Huang, Chi-Lin Teng, Hai-Ching Chen, Shao-Kuan Lee, Cheng-Chin Lee +1 more | 2022-05-03 |
| 11309241 | Protection liner on interconnect wire to enlarge processing window for overlying interconnect via | Shin-Yi Yang, Hsin-Yen Huang, Ming-Han Lee, Yu-Chen Chan, Meng-Pei Lu | 2022-04-19 |
| 11296026 | Semiconductor device and manufacturing method thereof | Ming-Han Lee | 2022-04-05 |
| 11251073 | Selective deposition of barrier layer | Hsin-Yen Huang, Hai-Ching Chen | 2022-02-15 |
| 11227833 | Interconnect structure and method for forming the same | Shao-Kuan Lee, Cheng-Chin Lee, Hsin-Yen Huang, Hai-Ching Chen | 2022-01-18 |
| 11222843 | Interconnect structure and method for forming the same | Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hai-Ching Chen | 2022-01-11 |
| 11211256 | Method with CMP for metal ion prevention | Shih-Kang Fu, Ming-Han Lee | 2021-12-28 |
| 11205618 | Graphene barrier layer | Shin-Yi Yang, Ming-Han Lee | 2021-12-21 |
| 11201106 | Semiconductor device with conductors embedded in a substrate | Hsin-Ping Chen, Ming-Han Lee | 2021-12-14 |
| 11189560 | Semiconductor device comprising etch stop layer over dielectric layer and method of manufacture | Shao-Kuan Lee, Hai-Ching Chen, Hsin-Yen Huang, Cheng-Chin Lee | 2021-11-30 |
| 11167984 | Nano-electromechanical system (NEMS) device structure and method for forming the same | Hsin-Ping Chen, Carlos H. Diaz, Ken-Ichi Goto, Tai-I Yang | 2021-11-09 |
| 11152255 | Methods of performing chemical-mechanical polishing process in semiconductor devices | Shih-Kang Fu, Ming-Han Lee | 2021-10-19 |
| 11127680 | Semiconductor device and manufacturing method thereof | Shih-Kang Fu, Hsien-Chang Wu, Li-Lin Su, Ming-Han Lee | 2021-09-21 |
| 11114374 | Graphene enabled selective barrier layer formation | Shin-Yi Yang, Guanyu Luo, Chin-Lung Chung, Ming-Han Lee | 2021-09-07 |
| 11094631 | Graphene layer for reduced contact resistance | Shin-Yi Yang, Ming-Han Lee | 2021-08-17 |
| 11094626 | Methods of forming interconnect structures in semiconductor fabrication | Ming-Han Lee | 2021-08-17 |
| 11087994 | Via connection to a partially filled trench | Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee +1 more | 2021-08-10 |