Issued Patents All Time
Showing 76–100 of 365 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11756878 | Self-aligned via structure by selective deposition | Shao-Kuan Lee, Hsin-Yen Huang, Cheng-Chin Lee, Hai-Ching Chen | 2023-09-12 |
| 11749643 | Semiconductor packages and methods for forming the same | Shin-Yi Yang, Ming-Han Lee | 2023-09-05 |
| 11742239 | Methods of performing chemical-mechanical polishing process in semiconductor devices | Shih-Kang Fu, Ming-Han Lee | 2023-08-29 |
| 11735513 | Integrated chip having a back-side power rail | Shin-Yi Yang, Ming-Han Lee | 2023-08-22 |
| 11728264 | Hybrid interconnect structure for self aligned via | Shin-Yi Yang, Ming-Han Lee | 2023-08-15 |
| 11721627 | Graphene layer for reduced contact resistance | Shin-Yi Yang, Ming-Han Lee | 2023-08-08 |
| 11715689 | Method of forming metal interconnection | Shin-Yi Yang, Ming-Han Lee, Tz-Jun Kuo | 2023-08-01 |
| 11710700 | Graphene-assisted low-resistance interconnect structures and methods of formation thereof | Shin-Yi Yang, Yu-Chen Chan, Ming-Han Lee, Hai-Ching Chen | 2023-07-25 |
| 11670595 | Semiconductor device structure and methods of forming the same | Yu-Chen Chan, Shu-Wei Li, Shin-Yi Yang, Ming-Han Lee | 2023-06-06 |
| 11658092 | Thermal interconnect structure for thermal management of electrical interconnect structure | Shao-Kuan Lee, Cherng-Shiaw Tsai, Ting-Ya Lo, Cheng-Chin Lee, Chi-Lin Teng +3 more | 2023-05-23 |
| 11652055 | Interconnect structure with hybrid barrier layer | Shu-Wei Li, Shin-Yi Yang, Ming-Han Lee | 2023-05-16 |
| 11640940 | Methods of forming interconnection structure including conductive graphene layers | Shu-Wei Li, Yu-Chen Chan, Shin-Yi Yang, Ming-Han Lee | 2023-05-02 |
| 11640928 | Heat dispersion layers for double sided interconnect | Hsin-Yen Huang, Shao-Kuan Lee, Hsiao-Kang Chang, Cherng-Shiaw Tsai | 2023-05-02 |
| 11640924 | Structure and method for interconnection with self-alignment | Tai-I Yang, Yu-Chieh Liao, Chia-Tien Wu, Hsin-Ping Chen, Hai-Ching Chen | 2023-05-02 |
| 11594483 | Semiconductor structure | Shin-Yi Yang, Ming-Han Lee | 2023-02-28 |
| 11569124 | Interconnect structure having an etch stop layer over conductive lines | Cheng-Hsiung Tsai, Chung-Ju Lee, Tien-I Bao | 2023-01-31 |
| 11557511 | Semiconductor device structure and methods of forming the same | Hsin-Yen Huang, Ting-Ya Lo, Shao-Kuan Lee, Chi-Lin Teng, Cheng-Chin Lee +1 more | 2023-01-17 |
| 11545389 | Titanium-containing diffusion barrier for CMP removal rate enhancement and contamination reduction | Shih-Kang Fu, Ming-Han Lee | 2023-01-03 |
| 11538749 | Interconnect structure | Shao-Kuan Lee, Hsin-Yen Huang, Cheng-Chin Lee, Kuang-Wei YANG, Ting-Ya Lo +2 more | 2022-12-27 |
| 11532552 | Method and apparatus for forming self-aligned via with selectively deposited etching stop layer | Yung-Hsu Wu, Hai-Ching Chen, Jung-Hsun Tsai, Tien-I Bao | 2022-12-20 |
| 11527435 | Metal capping layer and methods thereof | Shao-Kuan Lee, Cheng-Chin Lee, Hsin-Yen Huang, Hai-Ching Chen | 2022-12-13 |
| 11482451 | Interconnect structures | Guanyu Luo, Shin-Yi Yang, Ming-Han Lee | 2022-10-25 |
| 11482447 | Method of forming an integrated chip having a cavity between metal features | Hsi-Wen Tien, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Yu-Teng Dai +1 more | 2022-10-25 |
| 11462470 | Method of forming graphene and metallic cap and barrier layers for interconnects | Shin-Yi Yang, Ming-Han Lee | 2022-10-04 |
| 11450602 | Hybrid method for forming semiconductor interconnect structure | Shih-Kang Fu, Ming-Han Lee | 2022-09-20 |