Issued Patents All Time
Showing 226–250 of 365 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9129906 | Self-aligned double spacer patterning process | Yung-Hsu Wu, Tsung-Min Huang, Cheng-Hsiung Tsai, Chung-Ju Lee, Tien-I Bao | 2015-09-08 |
| 9123776 | Self-aligned double spacer patterning process | Cheng-Hsiung Tsai, Yung-Hsu Wu, Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao | 2015-09-01 |
| 9095995 | Method of forming multiple patterning spacer structures | Chih Wei Lu, Chung-Ju Lee | 2015-08-04 |
| 9040417 | Semiconductor devices and methods of manufacture thereof | Hsin-Chieh Yao, Chung-Ju Lee, Tien-I Bao | 2015-05-26 |
| 9030013 | Interconnect structures comprising flexible buffer layers | Chao-Hsien Peng, Hsin-Yen Huang, Hsiang-Huan Lee | 2015-05-12 |
| 8941239 | Copper interconnect structure and method for forming the same | Chen-Hua Yu, Hsiang-Huan Lee, Ching-Fu Yeh | 2015-01-27 |
| 8916469 | Method of fabricating copper damascene | Chao-Hsien Peng, Chi-Liang Kuo, Hsiang-Huan Lee | 2014-12-23 |
| 8912041 | Method for forming recess-free interconnect structure | Chao-Hsien Peng, Hsiang-Huan Lee | 2014-12-16 |
| 8889544 | Dielectric protection layer as a chemical-mechanical polishing stop layer | Yung-Hsu Wu, Hsin-Hsien Lu, Tien-I Bao | 2014-11-18 |
| 8841773 | Multi-layer interconnect structure for stacked dies | Hung-Pin Chang, Chien-Ming Chiu, Tsang-Jiuh Wu, Chen-Hua Yu | 2014-09-23 |
| 8836127 | Interconnect with flexible dielectric layer | Ching-Yu Lo, Bo-Jiun Lin, Hai-Ching Chen, Tien-I Bao, Chen-Hua Yu | 2014-09-16 |
| 8791011 | Through-silicon via structure formation process | Yung-Chi Lin, Weng-Jin Wu | 2014-07-29 |
| 8791528 | Methods of manufacturing metal-silicide features | Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chaing-Ming Chuang | 2014-07-29 |
| 8791549 | Wafer backside interconnect structure connected to TSVs | Ming-Fa Chen, Wen-Chih Chiou | 2014-07-29 |
| 8723275 | Semiconductor device with metal silicides having different phases | Wei-Jung Lin, Cheng-Tung Lin, Chih-Wei Chang | 2014-05-13 |
| 8647925 | Surface modification for handling wafer thinning process | Wen-Chih Chiou, Weng-Jin Wu, Ju-Pin Hung | 2014-02-11 |
| 8629058 | Methods for via structure with improved reliability | Cheng-Lin Huang, Ching-Hua Hsieh | 2014-01-14 |
| 8624396 | Apparatus and method for low contact resistance carbon nanotube interconnect | Hsien-Chang Wu, Hsiang-Huan Lee | 2014-01-07 |
| 8466059 | Multi-layer interconnect structure for stacked dies | Hung-Pin Chang, Chien-Ming Chiu, Tsang-Jiuh Wu, Chen-Hua Yu | 2013-06-18 |
| 8441136 | Protection layer for adhesive material at wafer edge | Wen-Chih Chiou, Weng-Jin Wu | 2013-05-14 |
| 8410607 | Semiconductor memory structures | Chao-An Jong | 2013-04-02 |
| 8405201 | Through-silicon via structure | Yung-Chi Lin, Weng-Jin Wu | 2013-03-26 |
| 8348719 | Polisher for chemical mechanical planarization | Hsin-Hsien Lu, Liang-Guang Chen, Tien-I Bao | 2013-01-08 |
| 8349730 | Transitional interface between metal and dielectric in interconnect structures | Chien-Hsueh Shih | 2013-01-08 |
| 8277619 | Apparatus for electrochemical plating semiconductor wafers | Chung-Liang Chang | 2012-10-02 |