Issued Patents All Time
Showing 276–300 of 365 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7432559 | Silicide formation on SiGe | Jerry Lai, Chii-Ming Wu, Chih-Wei Chang | 2008-10-07 |
| 7423347 | In-situ deposition for cu hillock suppression | Chung-Hsien Chen, Chun-Chieh Lin, Minghsing Tsai | 2008-09-09 |
| 7405151 | Method for forming a semiconductor device | Gin Jei Wang, Chao-Hsien Peng, Chii-Ming Wu, Chih-Wei Chang | 2008-07-29 |
| 7396767 | Semiconductor structure including silicide regions and method of making same | Chii-Ming Wu, Cheng-Tung Lin, Mei-Yun Wang, Chih-Wei Chang | 2008-07-08 |
| 7354856 | Method for forming dual damascene structures with tapered via portions and improved performance | Ming-Shih Yeh, Ming-Hsing Tsai, Chen-Hua Yu | 2008-04-08 |
| 7338903 | Sequential reducing plasma and inert plasma pre-treatment method for oxidizable conductor layer | Chao-Hsien Peng, Jing-Cheng Lin, Ching-Hua Hsieh | 2008-03-04 |
| 7312531 | Semiconductor device and fabrication method thereof | Hui-Lin Chang, Yung-Cheng Lu, Chung-Chi Ko, Pi-Tsung Chen, Chien-Hsueh Shih +2 more | 2007-12-25 |
| 7282450 | Sidewall coverage for copper damascene filling | Mei-Yun Wang, Chen-Hua Yu | 2007-10-16 |
| 7268065 | Methods of manufacturing metal-silicide features | Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang | 2007-09-11 |
| 7265038 | Method for forming a multi-layer seed layer for improved Cu ECP | Ping-Kun Wu, Horng-Huei Tseng, Chine-Gie Lo, Chao-Hsiung Wang | 2007-09-04 |
| 7259463 | Damascene interconnect structure with cap layer | Jui Jen Huang, Minghsing Tsai, Hung-Wen Su, Ting-Chu Ko | 2007-08-21 |
| 7256137 | Method of forming contact plug on silicide structure | Chii-Ming Wu, Chih-Wei Chang, Ju-Wang Hsu, Ming-Huan Tsai | 2007-08-14 |
| 7253501 | High performance metallization cap layer | Hsien-Ming Lee, Jing-Cheng Lin, Shing-Chyang Pan, Ching-Hua Hsieh, Chao-Hsien Peng +2 more | 2007-08-07 |
| 7250683 | Method to solve via poisoning for porous low-k dielectric | Ming-Hsing Tsai, Jing-Cheng Lin, Chen-Hua Yu | 2007-07-31 |
| 7247915 | Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology | Chih-Wei Chang, Mei-Yun Wang, Mong-Song Liang | 2007-07-24 |
| 7235482 | Method of manufacturing a contact interconnection layer containing a metal and nitrogen by atomic layer deposition for deep sub-micron semiconductor technology | Chii-Ming Wu, Ming-Hsing Tsai, Ching-Hua Hsieh | 2007-06-26 |
| 7226860 | Method and apparatus for fabricating metal layer | Hsien-Ming Lee, Jing-Cheng Lin, Shing-Chyang Pan, Ming-Hsing Tsai, Hung-Wen Su +3 more | 2007-06-05 |
| 7215024 | Barrier-less integration with copper alloy | Jing-Cheng Lin, Cheng-Lin Huang, Ching-Hua Hsieh, Mong-Song Liang | 2007-05-08 |
| 7205234 | Method of forming metal silicide | Chii-Ming Wu, Mei-Yun Wang, Chih-Wei Chang | 2007-04-17 |
| 7202162 | Atomic layer deposition tantalum nitride layer to improve adhesion between a copper structure and overlying materials | Jing-Cheng Lin, Chao-Hsien Peng, Mong-Song Liang | 2007-04-10 |
| 7193327 | Barrier structure for semiconductor devices | Chen-Hua Yu, Shing-Chyang Pan, Ching-Hua Hsieh, Cheng-Lin Huang, Hsien-Ming Lee +1 more | 2007-03-20 |
| 7179759 | Barrier layer and fabrication method thereof | Cheng-Lin Huang, Ching-Hua Hsieh | 2007-02-20 |
| 7105439 | Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology | Chih-Wei Chang, Mei-Yun Wang, Mong-Song Liang | 2006-09-12 |
| 7091600 | Prevention of post CMP defects in CU/FSG process | Chung-Shi Liu | 2006-08-15 |
| 7078810 | Semiconductor device and fabrication method thereof | Gin Jie Wang, Chao-Hsien Peng, Chii-Ming Wu, Chih-Wei Chang | 2006-07-18 |