Issued Patents All Time
Showing 376–400 of 482 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10304940 | Gate cut and fin trim isolation for advanced integrated circuit structure fabrication | Byron Ho, Michael L. Hattendorf, Christopher P. Auth | 2019-05-28 |
| 10304946 | Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices | Rishabh Mehandru, Patrick Morrow, Ranjith Kumar, Cory E. Weber, Seiyon Kim +1 more | 2019-05-28 |
| 10297670 | Contact resistance reduction employing germanium overlayer pre-contact metalization | Glenn A. Glass, Anand S. Murthy | 2019-05-21 |
| 10290709 | Apparatus and methods to create an indium gallium arsenide active channel having indium rich surfaces | Glenn A. Glass, Anand S. Murthy, Chandra S. Mohapatra, Willy Rachmady, Gilbert Dewey +2 more | 2019-05-14 |
| 10283589 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Kelin J. Kuhn, Anand S. Murthy, Mark Armstrong, Rafael Rios +2 more | 2019-05-07 |
| 10263036 | Strain assisted spin torque switching spin transfer torque memory | Sasikanth Manipatruni, Dmitri E. Nikonov, Asif Khan, Raseong Kim, Ian A. Young | 2019-04-16 |
| 10243078 | Carrier confinement for high mobility channel devices | Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Willy Rachmady, Anand S. Murthy +3 more | 2019-03-26 |
| 10229981 | Gate-all-around (GAA) transistor with stacked nanowires on locally isolated substrate | Annalisa Cappellani, Abhijit Jayant Pethe, Harry Gomez | 2019-03-12 |
| 10229997 | Indium-rich NMOS transistor channels | Chandra S. Mohapatra, Anand S. Murthy, Glenn A. Glass, Willy Rachmady, Jack T. Kavalieros +3 more | 2019-03-12 |
| 10211208 | High-mobility semiconductor source/drain spacer | Gilbert Dewey, Matthew V. Metz, Anand S. Murthy, Willy Rachmady, Chandra S. Mohapatra +2 more | 2019-02-19 |
| 10192783 | Gate contact structure over active gate and method to fabricate same | Abhijit Jayant Pethe, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani | 2019-01-29 |
| 10170314 | Pulsed laser anneal process for transistor with partial melt of a raised source-drain | Jacob Jensen, Mark Liu, Harold W. Kennel, Robert James | 2019-01-01 |
| 10153372 | High mobility strained channels for fin-based NMOS transistors | Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Glenn A. Glass, Anand S. Murthy +1 more | 2018-12-11 |
| 10147817 | Techniques for integration of Ge-rich p-MOS source/drain | Glenn A. Glass, Anand S. Murthy, Ying-Feng PANG, Nabil G. Mistkawi | 2018-12-04 |
| 10141226 | Self-aligned contacts | Mark Bohr, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus +2 more | 2018-11-27 |
| 10121856 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Kelin J. Kuhn, Anand S. Murthy, Mark Armstrong, Rafael Rios +2 more | 2018-11-06 |
| 10109711 | CMOS FinFET device having strained SiGe fins and a strained Si cladding layer on the NMOS channel | Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass +1 more | 2018-10-23 |
| 10084043 | High mobility nanowire fin channel on silicon substrate formed using sacrificial sub-fin | Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Willy Rachmady, Anand S. Murthy +4 more | 2018-09-25 |
| 10074573 | CMOS nanowire structure | Seiyon Kim, Kelin J. Kuhn, Anand S. Murthy, Annalisa Cappellani, Stephen M. Cea +2 more | 2018-09-11 |
| 10056380 | Non-planar semiconductor device having doped sub-fin region and method to fabricate same | Salman Latif, Chanaka D. Munasinghe | 2018-08-21 |
| 10026829 | Semiconductor device with isolated body portion | Annalisa Cappellani, Stephen M. Cea, Harry Gomez, Jack T. Kavalieros, Patrick H. Keys +5 more | 2018-07-17 |
| 9997563 | Logic chip including embedded magnetic tunnel junctions | Kevin J. Lee, Joseph M. Steigerwald, John H. Epple, Yih Wang | 2018-06-12 |
| 9935107 | CMOS FinFET device with dual strained cladding layers on relaxed SiGe fins, and method of fabricating the same | Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Kelin J. Kuhn | 2018-04-03 |
| 9929273 | Apparatus and methods of forming fin structures with asymmetric profile | Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Gilbert Dewey, Nadia M. Rahhal-Orabi +3 more | 2018-03-27 |
| 9923054 | Fin structure having hard mask etch stop layers underneath gate sidewall spacers | Ritesh Jhaveri, Bernard Sell | 2018-03-20 |