Issued Patents All Time
Showing 401–425 of 482 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9892967 | Self-aligned contacts | Mark Bohr, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus +2 more | 2018-02-13 |
| 9893149 | High mobility strained channels for fin-based transistors | Stephen M. Cea, Anand S. Murthy, Glenn A. Glass, Daniel B. Aubertine, Jack T. Kavalieros +1 more | 2018-02-13 |
| 9882027 | Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions | Szuya S. Liao, Michael L. Hattendorf | 2018-01-30 |
| 9876016 | Wrap-around trench contact structure and methods of fabrication | Joseph M. Steigerwald, Oleg Golonzka | 2018-01-23 |
| 9859424 | Techniques for integration of Ge-rich p-MOS source/drain contacts | Glenn A. Glass, Anand S. Murthy, Ying-Feng PANG, Nabil G. Mistkawi | 2018-01-02 |
| 9859368 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Kelin J. Kuhn, Anand S. Murthy, Mark Armstrong, Rafael Rios +2 more | 2018-01-02 |
| 9831306 | Self-aligned gate edge and local interconnect and method to fabricate same | Milton Clair Webb, Mark Bohr, Szuya S. Liao | 2017-11-28 |
| 9761713 | Multi-threshold voltage devices and associated techniques and configurations | Joseph M. Steigerwald, Jenny Hu, Ian R. Post | 2017-09-12 |
| 9754940 | Self-aligned contact metallization for reduced contact resistance | Glenn A. Glass, Anand S. Murthy | 2017-09-05 |
| 9735270 | Semiconductor transistor having a stressed channel | Anand S. Murthy, Robert S. Chau, Kaizad Mistry | 2017-08-15 |
| 9728464 | Self-aligned 3-D epitaxial structures for MOS device fabrication | Glenn A. Glass, Daniel B. Aubertine, Anand S. Murthy, Gaurav Thareja | 2017-08-08 |
| 9722023 | Selective germanium P-contact metalization through trench | Glenn A. Glass, Anand S. Murthy | 2017-08-01 |
| 9716037 | Gate aligned contact and method to fabricate same | Oleg Golonzka, Swaminathan Sivakumar, Charles H. Wallace | 2017-07-25 |
| 9705000 | III-V layers for n-type and p-type MOS source-drain contacts | Glenn A. Glass, Anand S. Murthy | 2017-07-11 |
| 9680013 | Non-planar device having uniaxially strained semiconductor body and method of making same | Stephen M. Cea, Roza Kotlyar, Jack T. Kavalieros, Martin D. Giles, Kelin J. Kuhn +2 more | 2017-06-13 |
| 9660181 | Logic chip including embedded magnetic tunnel junctions | Kevin J. Lee, Joseph M. Steigerwald, John H. Epple, Yih Wang | 2017-05-23 |
| 9627384 | Transistors with high concentration of boron doped germanium | Anand S. Murthy, Glenn A. Glass, Ravi Pillarisetty, Niloy Mukherjee, Jack T. Kavalieros +3 more | 2017-04-18 |
| 9607987 | Methods for forming fins for metal oxide semiconductor device structures | Martin D. Giles | 2017-03-28 |
| 9608059 | Semiconductor device with isolated body portion | Annalisa Cappellani, Stephen M. Cea, Harry Gomez, Jack T. Kavalieros, Patrick H. Keys +5 more | 2017-03-28 |
| 9583491 | CMOS nanowire structure | Seiyon Kim, Kelin J. Kuhn, Anand S. Murthy, Annalisa Cappellani, Stephen M. Cea +2 more | 2017-02-28 |
| 9577057 | Semiconductor device contacts | Michael Haverty, Sadasivan Shankar, Seongjun Park | 2017-02-21 |
| 9508821 | Self-aligned contacts | Mark Bohr, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus +2 more | 2016-11-29 |
| 9490364 | Semiconductor transistor having a stressed channel | Anand S. Murthy, Robert S. Chau, Kaizad Mistry | 2016-11-08 |
| 9484432 | Contact resistance reduction employing germanium overlayer pre-contact metalization | Glenn A. Glass, Anand S. Murthy | 2016-11-01 |
| 9484272 | Methods for fabricating strained gate-all-around semiconductor devices by fin oxidation using an undercut etch-stop layer | Annalisa Cappellani, Abhijit Jayant Pethe, Harry Gomez | 2016-11-01 |