| 10522510 |
Heterogeneous integration of ultrathin functional block by solid phase adhesive and selective transfer |
Kimin Jun, Jacob Jensen, Paul B. Fischer |
2019-12-31 |
$25,528,000 |
| 10490542 |
Integrated circuit layout using library cells with alternating conductive lines |
Donald W. Nelson, Steven M. Burns |
2019-11-26 |
$25,149,000 |
| 10490449 |
Techniques for revealing a backside of an integrated circuit device, and associated configurations |
Il-Seok Son, Colin T. Carver, Paul B. Fischer, Kimin Jun |
2019-11-26 |
$25,149,000 |
| 10483321 |
High density memory architecture using back side metal layers |
Yih Wang |
2019-11-19 |
$26,843,000 |
| 10468489 |
Isolation structures for an integrated circuit element and method of making same |
Aaron D. Lilak, Uygar E. Avci, David L. Kencke, Kerryann Marrietta Foley, Stephen M. Cea +1 more |
2019-11-05 |
$22,190,000 |
| 10453679 |
Methods and devices integrating III-N transistor circuitry with Si transistor circuitry |
Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Ravi Pillarisetty, Kimin Jun +3 more |
2019-10-22 |
$16,310,000 |
| 10439057 |
Multi-gate high electron mobility transistors and methods of fabrication |
Kimin Jun, Sansaptak Dasgupta, Alejandro X. Levander |
2019-10-08 |
$19,521,000 |
| 10396045 |
Metal on both sides of the transistor integrated with magnetic inductors |
Paul B. Fischer |
2019-08-27 |
$17,353,000 |
| 10367070 |
Methods of forming backside self-aligned vias and structures formed thereby |
Mauro J. Kobrinsky, Kimin Jun, Il-Seok Son, Paul B. Fischer |
2019-07-30 |
$29,864,000 |
| 10361090 |
Vertical channel transistors fabrication process by selective subtraction of a regular grid |
Kimin Jun, Donald W. Nelson |
2019-07-23 |
$32,139,000 |
| 10325840 |
Metal on both sides with power distributed through the silicon |
Donald W. Nelson, Mark Bohr |
2019-06-18 |
$21,210,000 |
| 10304946 |
Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices |
Rishabh Mehandru, Ranjith Kumar, Cory E. Weber, Seiyon Kim, Stephen M. Cea +1 more |
2019-05-28 |
$17,387,000 |
| 10297592 |
Monolithic three-dimensional (3D) ICs with local inter-level interconnects |
Kimin Jun, M. Clair Webb, Donald W. Nelson |
2019-05-21 |
$20,944,000 |
| 10236282 |
Partial layer transfer system and method |
Kimin Jun, Il-Seok Son, Rajashree Baskaran, Paul B. Fischer |
2019-03-19 |
$29,538,000 |
| 10186484 |
Metal on both sides with clock gated-power and signal routing underneath |
Donald W. Nelson, Kimin Jun |
2019-01-22 |
$27,645,000 |
| 10068874 |
Method for direct integration of memory die to logic die without use of thru silicon vias (TSV) |
Donald W. Nelson, M Clair Webb, Kimin Jun |
2018-09-04 |
$19,235,000 |
| 10043797 |
Techniques for forming vertical transistor architectures |
Kimin Jun |
2018-08-07 |
$25,284,000 |
| 10014374 |
Planar heterogeneous device |
Kimin Jun |
2018-07-03 |
$24,450,000 |
| 9935191 |
High electron mobility transistor fabrication process on reverse polarized substrate by layer transfer |
Kimin Jun, Sansaptak Dasgupta, Alejandro X. Levander |
2018-04-03 |
$16,515,000 |
| 9818751 |
Methods of forming buried vertical capacitors and structures formed thereby |
Rajashree Baskaran, Kimin Jun |
2017-11-14 |
$11,178,000 |
| 9793373 |
Field effect transistor structure with abrupt source/drain junctions |
Anand S. Murthy, Robert S. Chau, Chia-Hong Jan, Paul Packan |
2017-10-17 |
$9,876,000 |
| 9761514 |
Substrate for integrated circuit devices including multi-layer glass core and methods of making the same |
Qing Ma, Chuan Hu |
2017-09-12 |
$10,213,000 |
| 9721898 |
Methods of forming under device interconnect structures |
Don Nelson, M. Clair Webb, Kimin Jun, Il-Seok Son |
2017-08-01 |
$11,137,000 |
| 9685436 |
Monolithic three-dimensional (3D) ICs with local inter-level interconnects |
Kimin Jun, M. Clair Webb, Donald W. Nelson |
2017-06-20 |
$9,273,000 |
| 9646972 |
Methods of forming buried vertical capacitors and structures formed thereby |
Rajashree Baskaran, Kimin Jun |
2017-05-09 |
$10,144,000 |
