Issued Patents All Time
Showing 126–150 of 187 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10490449 | Techniques for revealing a backside of an integrated circuit device, and associated configurations | Il-Seok Son, Colin T. Carver, Paul B. Fischer, Kimin Jun | 2019-11-26 |
| 10483321 | High density memory architecture using back side metal layers | Yih Wang | 2019-11-19 |
| 10468489 | Isolation structures for an integrated circuit element and method of making same | Aaron D. Lilak, Uygar E. Avci, David L. Kencke, Kerryann Marrietta Foley, Stephen M. Cea +1 more | 2019-11-05 |
| 10453679 | Methods and devices integrating III-N transistor circuitry with Si transistor circuitry | Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Ravi Pillarisetty, Kimin Jun +3 more | 2019-10-22 |
| 10439057 | Multi-gate high electron mobility transistors and methods of fabrication | Kimin Jun, Sansaptak Dasgupta, Alejandro X. Levander | 2019-10-08 |
| 10396045 | Metal on both sides of the transistor integrated with magnetic inductors | Paul B. Fischer | 2019-08-27 |
| 10367070 | Methods of forming backside self-aligned vias and structures formed thereby | Mauro J. Kobrinsky, Kimin Jun, Il-Seok Son, Paul B. Fischer | 2019-07-30 |
| 10361090 | Vertical channel transistors fabrication process by selective subtraction of a regular grid | Kimin Jun, Donald W. Nelson | 2019-07-23 |
| 10325840 | Metal on both sides with power distributed through the silicon | Donald W. Nelson, Mark Bohr | 2019-06-18 |
| 10304946 | Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices | Rishabh Mehandru, Ranjith Kumar, Cory E. Weber, Seiyon Kim, Stephen M. Cea +1 more | 2019-05-28 |
| 10297592 | Monolithic three-dimensional (3D) ICs with local inter-level interconnects | Kimin Jun, M. Clair Webb, Donald W. Nelson | 2019-05-21 |
| 10236282 | Partial layer transfer system and method | Kimin Jun, Il-Seok Son, Rajashree Baskaran, Paul B. Fischer | 2019-03-19 |
| 10186484 | Metal on both sides with clock gated-power and signal routing underneath | Donald W. Nelson, Kimin Jun | 2019-01-22 |
| 10068874 | Method for direct integration of memory die to logic die without use of thru silicon vias (TSV) | Donald W. Nelson, M Clair Webb, Kimin Jun | 2018-09-04 |
| 10043797 | Techniques for forming vertical transistor architectures | Kimin Jun | 2018-08-07 |
| 10014374 | Planar heterogeneous device | Kimin Jun | 2018-07-03 |
| 9935191 | High electron mobility transistor fabrication process on reverse polarized substrate by layer transfer | Kimin Jun, Sansaptak Dasgupta, Alejandro X. Levander | 2018-04-03 |
| 9818751 | Methods of forming buried vertical capacitors and structures formed thereby | Rajashree Baskaran, Kimin Jun | 2017-11-14 |
| 9793373 | Field effect transistor structure with abrupt source/drain junctions | Anand S. Murthy, Robert S. Chau, Chia-Hong Jan, Paul Packan | 2017-10-17 |
| 9761514 | Substrate for integrated circuit devices including multi-layer glass core and methods of making the same | Qing Ma, Chuan Hu | 2017-09-12 |
| 9721898 | Methods of forming under device interconnect structures | Don Nelson, M. Clair Webb, Kimin Jun, Il-Seok Son | 2017-08-01 |
| 9685436 | Monolithic three-dimensional (3D) ICs with local inter-level interconnects | Kimin Jun, M. Clair Webb, Donald W. Nelson | 2017-06-20 |
| 9646972 | Methods of forming buried vertical capacitors and structures formed thereby | Rajashree Baskaran, Kimin Jun | 2017-05-09 |
| 9640634 | Field effect transistor structure with abrupt source/drain junctions | Anand S. Murthy, Robert S. Chau, Chia-Hong Jan, Paul Packan | 2017-05-02 |
| 9590051 | Heterogeneous layer device | Kimin Jun | 2017-03-07 |