Issued Patents All Time
Showing 176–187 of 187 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7129172 | Bonded wafer processing method | R. Scott List, Michael Chan | 2006-10-31 |
| 7056813 | Methods of forming backside connections on a wafer stack | R. Scott List, Sarah Kim | 2006-06-06 |
| 6992391 | Dual-damascene interconnects without an etch stop layer by alternating ILDs | Andrew Ott, Lawrence Wong, Jihperng Leu, Grant Kloster | 2006-01-31 |
| 6946384 | Stacked device underfill and a method of fabrication | Grant Kloster, Michael Goodner, Shriram Ramanathan | 2005-09-20 |
| 6897125 | Methods of forming backside connections on a wafer stack | R. Scott List, Sarah Kim | 2005-05-24 |
| 6887762 | Method of fabricating a field effect transistor structure with abrupt source/drain junctions | Anand S. Murthy, Robert S. Chau, Chia-Hong Jan, Paul Packan | 2005-05-03 |
| 6872666 | Method for making a dual damascene interconnect using a dual hard mask | — | 2005-03-29 |
| 6797556 | MOS transistor structure and method of fabrication | Anand S. Murthy, Robert S. Chau | 2004-09-28 |
| 6661094 | Semiconductor device having a dual damascene interconnect spaced from a support structure | Xiaorong Morrow | 2003-12-09 |
| 6541343 | Methods of making field effect transistor structure with partially isolated source/drain junctions | Anand S. Murthy, Robert S. Chau, Robert McFadden | 2003-04-01 |
| 6479391 | Method for making a dual damascene interconnect using a multilayer hard mask | Jihperng Leu, Chia-Hong Jan | 2002-11-12 |
| 6448177 | Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure | Xiaorong Morrow | 2002-09-10 |