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Patrick Morrow — 189 Patents

Intel: 188 patents #68 of 30,777Top 1%

INIntle: 1 patents #1 of 16Top 7%

Portland, OR: #31 of 9,213 inventorsTop 1%

Oregon: #66 of 28,073 inventorsTop 1%

Overall (All Time): #3,834 of 4,157,543Top 1%

189 Patents All Time

Patrick Morrow has been granted 189 US patents while listed as an inventor at Intel. The first was granted in 2002 and the most recent in December 2025. Patrick Morrow ranks #3,834 of 4,157,543 US inventors in our database (top 0.09%). Patent records list Patrick Morrow in Portland, OR, US.

Patents per Year

Issued Patents All Time

Showing 176–189 of 189 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
7214605	Deposition of diffusion barrier	Shriram Ramanathan, Grant Kloster, Vijayakumar Ramachandrarao, Scott List	2007-05-08	$17,693,000
7180180	Stacked device underfill and a method of fabrication	Grant Kloster, Michael Goodner, Shriram Ramanathan	2007-02-20	$9,940,000
7129172	Bonded wafer processing method	R. Scott List, Michael Chan	2006-10-31	$18,482,000
7056813	Methods of forming backside connections on a wafer stack	R. Scott List, Sarah Kim	2006-06-06	$10,284,000
6992391	Dual-damascene interconnects without an etch stop layer by alternating ILDs	Andrew Ott, Lawrence Wong, Jihperng Leu, Grant Kloster	2006-01-31	$19,938,000
6946384	Stacked device underfill and a method of fabrication	Grant Kloster, Michael Goodner, Shriram Ramanathan	2005-09-20	$19,561,000
6897125	Methods of forming backside connections on a wafer stack	R. Scott List, Sarah Kim	2005-05-24	$30,688,000
6887762	Method of fabricating a field effect transistor structure with abrupt source/drain junctions	Anand S. Murthy, Robert S. Chau, Chia-Hong Jan, Paul Packan	2005-05-03	$20,343,000
6872666	Method for making a dual damascene interconnect using a dual hard mask	—	2005-03-29	$48,968,000
6797556	MOS transistor structure and method of fabrication	Anand S. Murthy, Robert S. Chau	2004-09-28	$27,830,000
6661094	Semiconductor device having a dual damascene interconnect spaced from a support structure	Xiaorong Morrow	2003-12-09	$40,688,000
6541343	Methods of making field effect transistor structure with partially isolated source/drain junctions	Anand S. Murthy, Robert S. Chau, Robert McFadden	2003-04-01	$56,060,000
6479391	Method for making a dual damascene interconnect using a multilayer hard mask	Jihperng Leu, Chia-Hong Jan	2002-11-12	$72,895,000
6448177	Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure	Xiaorong Morrow	2002-09-10	$32,074,000