Issued Patents All Time
Showing 26–50 of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9753076 | Voltage rail monitoring to detect electromigration | David D. Cadigan, Adam J. McPadden, Anuwat Saetow, Gary A. Tressler | 2017-09-05 |
| 9746516 | Collecting diagnostic data from chips | Steven M. Douskey, Ryan A. Fitch, Mary P. Kusko | 2017-08-29 |
| 9697910 | Multi-match error detection in content addressable memory testing | Pradip Patel, Daniel Rodko | 2017-07-04 |
| 9627012 | Shift register with opposite shift data and shift clock directions | Norman K. James, Pradip Patel, Daniel Rodko | 2017-04-18 |
| 9557381 | Physically aware insertion of diagnostic circuit elements | Mary P. Kusko, Sridhar H. Rangarajan, Robert C. Redburn, Andrew A. Turner | 2017-01-31 |
| 9548773 | Mitigation of EMI/ESD-caused transmission errors on an electronic circuit | David D. Cadigan, Samuel R. Connor, Michael A. Cracraft, Adam J. McPadden, Anuwat Saetow +1 more | 2017-01-17 |
| 9372232 | Collecting diagnostic data from chips | Steven M. Douskey, Ryan A. Fitch, Mary P. Kusko | 2016-06-21 |
| 9355746 | Built-in testing of unused element on chip | Luiz C. Alves, William J. Clarke, Christopher R. Conklin, Kevin W. Kark, Thomas J. Knips +1 more | 2016-05-31 |
| 9285423 | Managing chip testing data | Steven M. Douskey, Ryan A. Fitch, Mary P. Kusko | 2016-03-15 |
| 9201727 | Error protection for a data bus | Kevin W. Kark, John G. Massey, K. Paul Muller, David L. Rude, David Wolpert | 2015-12-01 |
| 9136019 | Built-in testing of unused element on chip | Luiz C. Alves, William J. Clarke, Christopher R. Conklin, Kevin W. Kark, Thomas J. Knips +1 more | 2015-09-15 |
| 9043683 | Error protection for integrated circuits | Kevin W. Kark, John G. Massey, K. Paul Muller, David L. Rude, David Wolpert | 2015-05-26 |
| 9041428 | Placement of storage cells on an integrated circuit | Kevin W. Kark, John G. Massey, K. Paul Muller, David L. Rude, David Wolpert | 2015-05-26 |
| 9021328 | Shared error protection for register banks | Kevin W. Kark, John G. Massey, K. Paul Muller, David L. Rude, David Wolpert | 2015-04-28 |
| 8942052 | Complementary metal-oxide-semiconductor (CMOS) min/max voltage circuit for switching between multiple voltages | Michael Kugel, Juergen Pille, Rolf Sautter, Dieter Wendel | 2015-01-27 |
| 8327207 | Memory testing system | Kevin Duffy, Pradip Patel, Daniel Rodko | 2012-12-04 |
| 8117579 | LSSD compatibility for GSD unified global clock buffers | James D. Warnock, Wendel Dieter, David E. Lackey, Leon Sigal, Louis Bernard Bushard +1 more | 2012-02-14 |
| 8055960 | Self test apparatus for identifying partially defective memory | David J. Lund, Kenneth H. Marz, Bryan L. Mechtly, Pradip Patel | 2011-11-08 |
| 8001411 | Generating a local clock domain using dynamic controls | Sean Michael Carey, Christian Jacobi, Guenter Mayer, Timothy G. McNamara, Chung-Lung K. Shum +2 more | 2011-08-16 |
| 7793173 | Efficient memory product for test and soft repair of SRAM with redundancy | Tom Chang, Thomas J. Knips, Donald W. Plass | 2010-09-07 |
| 7752514 | Methods and apparatus for testing a scan chain to isolate defects | Leendert M. Huisman, Maroun Kassab, Franco Motika | 2010-07-06 |
| 7650535 | Array delete mechanisms for shipping a microprocessor with defective arrays | Norbert Hagspiel, Frank Lehnert, Brian R. Prasky, Richard F. Rizzolo, Rolf Sautter | 2010-01-19 |
| 7606060 | Eight transistor SRAM cell with improved stability requiring only one word line | Yuen H. Chan, Donald W. Plass | 2009-10-20 |
| 7536613 | BIST address generation architecture for multi-port memories | Pradip Patel, Daniel Rodko | 2009-05-19 |
| 7529997 | Method for self-correcting cache using line delete, data logging, and fuse repair correction | Patrick J. Meaney, Thomas J. Knips, David J. Lund, Bryan L. Mechtly, Pradip Patel | 2009-05-05 |