Issued Patents All Time
Showing 51–75 of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7478297 | Merged MISR and output register without performance impact for circuits under test | Yuen H. Chan, Pradip Patel, Daniel Rodko | 2009-01-13 |
| 7437626 | Efficient method of test and soft repair of SRAM with redundancy | Tom Chang, Thomas J. Knips, Donald W. Plass | 2008-10-14 |
| 7434130 | Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection | Leendert M. Huisman, Franco Motika, Leah Pastel | 2008-10-07 |
| 7400555 | Built in self test circuit for measuring total timing uncertainty in a digital data path | Robert L. Franch, Norman K. James, Phillip J. Restle, Timothy M. Skergan | 2008-07-15 |
| 7368958 | Methods and systems for locally generating non-integral divided clocks with centralized state machines | Charlie C. Hwang, Timothy G. McNamara | 2008-05-06 |
| 7366953 | Self test method and apparatus for identifying partially defective memory | David J. Lund, Kenneth H. Marz, Bryan L. Mechtly, Pradip Patel | 2008-04-29 |
| 7355460 | Method for locally generating non-integral divided clocks with centralized state machines | Charlie C. Hwang, Timothy G. McNamara | 2008-04-08 |
| 7319348 | Circuits for locally generating non-integral divided clocks with centralized state machines | Charlie C. Hwang, Timothy C. McNamara | 2008-01-15 |
| 7313744 | Methods and apparatus for testing a scan chain to isolate defects | Leendert M. Huisman, Maroun Kassab, Franco Motika | 2007-12-25 |
| 7305602 | Merged MISR and output register without performance impact for circuits under test | Yuen H. Chan, Pradip Patel, Daniel Rodko | 2007-12-04 |
| 7295458 | Eight transistor SRAM cell with improved stability requiring only one word line | Yuen H. Chan, Donald W. Plass | 2007-11-13 |
| 7275194 | Clock duty cycle based access timer combined with standard stage clocked output register | Pradip Patel, Daniel Rodko | 2007-09-25 |
| 7260757 | System and method for testing electronic devices on a microchip | Franco Motika | 2007-08-21 |
| 7257745 | Array self repair using built-in self test techniques | Franco Motika, Pradip Patel, Daniel Rodko | 2007-08-14 |
| 7219275 | Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of SRAM with redundancy | Tom Chang, Thomas J. Knips, Donald W. Plass | 2007-05-15 |
| 7178075 | High-speed level sensitive scan design test scheme with pipelined test clocks | James D. Warnock | 2007-02-13 |
| 7139944 | Method and system for determining minimum post production test time required on an integrated circuit device to achieve optimum reliability | Tange Barbour, Thomas S. Barnett, Matthew S. Grady, Michael R. Ouellette | 2006-11-21 |
| 7129764 | System and method for local generation of a ratio clock | Timothy G. McNamara | 2006-10-31 |
| 7099201 | Multifunctional latch circuit for use with both SRAM array and self test device | Andrew James Bianchi, Yuen H. Chan, Michael Ju Hyeok Lee, Edelmar Seewann, Philip G. Shephard, III | 2006-08-29 |
| 6978408 | Generating array bit-fail maps without a tester using on-chip trace arrays | Norman K. James | 2005-12-20 |
| 6912665 | Automatic timing analyzer | Wayne F. Ellis, John A. Fifield, Louis Hsu | 2005-06-28 |
| 6865501 | Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection | Leendert M. Huisman, Franco Motika, Leah Pfeifer Pastel | 2005-03-08 |
| 6836865 | Method and apparatus for facilitating random pattern testing of logic structures | Mary P. Kusko, Bryan J. Robbins, Timothy Charest | 2004-12-28 |
| 6728914 | Random path delay testing methodology | Kevin William McCauley, Mary P. Kusko, Peilin Song, Richard F. Rizzolo, Ulrich Baur +1 more | 2004-04-27 |
| 6671644 | Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection | Leendert M. Huisman, Franco Motika, Leah Pastel | 2003-12-30 |