Issued Patents All Time
Showing 1–25 of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12174251 | System testing using partitioned and controlled noise | Mary P. Kusko, Eugene Atwood, Dustin Feller | 2024-12-24 |
| 11817697 | Method to limit the time a semiconductor device operates above a maximum operating voltage | Adam B. Collura, Michael Romain, Pawel Owczarczyk, Christian Jacobi, Anthony Saporito +9 more | 2023-11-14 |
| 11657887 | Testing bit write operation to a memory array in integrated circuits | Thomas J. Knips, Uma Srinivasan, Daniel Rodko, Matthew Steven Hyde | 2023-05-23 |
| 11462295 | Microchip level shared array repair | Timothy Erickson Meehan, Kirk D. Peterson, John Bradley Deforge, Uma Srinivasan, Hyong Uk Kim +2 more | 2022-10-04 |
| 11169841 | Tunable power save loop for processor chips | K Paul Muller, Eberhard Engler, Christopher R. Conklin, Stephanie Lehrer, Andrew A. Turner | 2021-11-09 |
| 10998075 | Built-in self-test for bit-write enabled memory arrays | Daniel Rodko, Pradip Patel, Matthew Steven Hyde | 2021-05-04 |
| 10971242 | Sequential error capture during memory test | Daniel Rodko, Pradip Patel | 2021-04-06 |
| 10949295 | Implementing dynamic SEU detection and correction method and circuit | Adam J. McPadden, Anuwat Saetow, David D. Cadigan | 2021-03-16 |
| 10897239 | Granular variable impedance tuning | Anuwat Saetow, David D. Cadigan, Adam J. McPadden | 2021-01-19 |
| 10896081 | Implementing SEU detection method and circuit | David D. Cadigan, Anuwat Saetow, Adam J. McPadden | 2021-01-19 |
| 10890623 | Power saving scannable latch output driver | Yuen H. Chan, Pradip Patel, Daniel Rodko | 2021-01-12 |
| 10585672 | Memory device command-address-control calibration | David D. Cadigan, Stephen P. Glancy, Kyu-hyoun Kim, Adam J. McPadden, Anuwat Saetow +1 more | 2020-03-10 |
| 10371747 | Physically aware scan diagnostic logic and power saving circuit insertion | Ankit N. Kagliwal, Mary P. Kusko, Robert C. Redburn | 2019-08-06 |
| 10373678 | SRAM margin recovery during burn-in | Chandrasekharan Kothandaraman, Adam J. McPadden, Uma Srinivasan, Stephen Wu | 2019-08-06 |
| 10332591 | SRAM margin recovery during burn-in | Chandrasekharan Kothandaraman, Adam J. McPadden, Uma Srinivasan, Stephen Wu | 2019-06-25 |
| 10324879 | Mitigation of side effects of simultaneous switching of input/output (I/O data signals | David D. Cadigan, Samuel R. Connor, Michael A. Cracraft, Adam J. McPadden, Anuwat Saetow +1 more | 2019-06-18 |
| 10229738 | SRAM bitline equalization using phase change material | David D. Cadigan, Adam J. McPadden, Anuwat Saetow | 2019-03-12 |
| 10163493 | SRAM margin recovery during burn-in | Chandrasekharan Kothandaraman, Adam J. McPadden, Uma Srinivasan, Stephen Wu | 2018-12-25 |
| 10157672 | SRAM bitline equalization using phase change material | David D. Cadigan, Adam J. McPadden, Anuwat Saetow | 2018-12-18 |
| 10061886 | Physically aware test patterns in semiconductor fabrication | Kevin M. McIvain, Samir Patel, Gary A. Van Huben | 2018-08-28 |
| 9983261 | Partition-able storage of test results using inactive storage elements | Thomas J. Knips, Pradip Patel, Daniel Rodko | 2018-05-29 |
| 9922163 | Physically aware test patterns in semiconductor fabrication | Kevin M. McIvain, Samir Patel, Gary A. Van Huben | 2018-03-20 |
| 9857416 | Voltage rail monitoring to detect electromigration | David D. Cadigan, Adam J. McPadden, Anuwat Saetow, Gary A. Tressler | 2018-01-02 |
| 9762212 | Initializing scannable and non-scannable latches from a common clock buffer | Ricardo H. Nigaglioni, Hagen Schmidt, James D. Warnock | 2017-09-12 |
| 9762213 | Initializing scannable and non-scannable latches from a common clock buffer | Ricardo H. Nigaglioni, Hagen Schmidt, James D. Warnock | 2017-09-12 |