Issued Patents All Time
Showing 351–375 of 1,139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11177367 | Self-aligned bottom spacer EPI last flow for VTFET | Tao Li, Sung-Dae Suk, Heng Wu | 2021-11-16 |
| 11177370 | Vertical field effect transistor with self-aligned source and drain top junction | Chun-Chen Yeh, Alexander Reznicek, Chen Zhang | 2021-11-16 |
| 11177632 | Augmented semiconductor lasers with spontaneous emissions blockage | Julien Frougier, Kangguo Cheng, Chanro Park | 2021-11-16 |
| 11171044 | Planarization controllability for interconnect structures | Chanro Park, Kangguo Cheng, Julien Frougier, Chih-Chao Yang | 2021-11-09 |
| 11164870 | Stacked upper fin and lower fin transistor with separate gate | Heng Wu, Chun Wing Yeung, Lan Yu | 2021-11-02 |
| 11164947 | Wrap around contact formation for VTFET | Heng Wu, Shogo Mochizuki, Lan Yu | 2021-11-02 |
| 11164960 | Transistor having in-situ doped nanosheets with gradient doped channel regions | Jingyun Zhang, Alexander Reznicek | 2021-11-02 |
| 11164787 | Two-stage top source drain epitaxy formation for vertical field effect transistors enabling gate last formation | Alexander Reznicek, Chun-Chen Yeh, Zuoguang Liu | 2021-11-02 |
| 11164792 | Complementary field-effect transistors | Alexander Reznicek, Jingyun Zhang, Junli Wang | 2021-11-02 |
| 11164782 | Self-aligned gate contact compatible cross couple contact formation | Balasubramanian S. Pranatharthi Haran, Dechao Guo, Nicolas Loubet, Alexander Reznicek | 2021-11-02 |
| 11164793 | Reduced source/drain coupling for CFET | Alexander Reznicek, Chanro Park, Chun-Chen Yeh | 2021-11-02 |
| 11164867 | Fin-type field-effect transistors over one or more buried polycrystalline layers | Siva P. Adusumilli, Julien Frougier, Anthony K. Stamper | 2021-11-02 |
| 11158544 | Vertical stacked nanosheet CMOS transistors with different work function metals | Kangguo Cheng, Juntao Li, Chanro Park | 2021-10-26 |
| 11158636 | Nanosheet device integrated with a FINFET transistor | Chun-Chen Yeh, Alexander Reznicek | 2021-10-26 |
| 11158543 | Silicide formation for source/drain contact in a vertical transport field-effect transistor | Heng Wu, Su Chen Fan, Huai Huang | 2021-10-26 |
| 11152265 | Local isolation of source/drain for reducing parasitic capacitance in vertical field effect transistors | Hemanth Jagannathan, Christopher J. Waskiewicz, Alexander Reznicek | 2021-10-19 |
| 11152464 | Self-aligned isolation for nanosheet transistor | Balasubramanian S. Pranatharthi Haran, Veeraraghavan S. Basker, Robert R. Robison | 2021-10-19 |
| 11139372 | Dual step etch-back inner spacer formation | Andrew M. Greene, Yao Yao, Veeraraghavan S. Basker | 2021-10-05 |
| 11139399 | Vertical transistor with self-aligned gate | Juntao Li, Kangguo Cheng, Chanro Park | 2021-10-05 |
| 11139242 | Via-to-metal tip connections in multi-layer chips | Chih-Chao Yang, Chi-Chun Liu, Kangguo Cheng | 2021-10-05 |
| 11131647 | Ion-sensitive field-effect transistor with sawtooth well to enhance sensitivity | Chanro Park, Kangguo Cheng, Juntao Li | 2021-09-28 |
| 11133217 | Late gate cut with optimized contact trench size | Alexander Reznicek, Balasubramanian S. Pranatharthi Haran, Praneet Adusumilli | 2021-09-28 |
| 11133308 | Uniform work function metal recess for vertical transistor complementary metal oxide semiconductor technology | Muthumanickam Sankarapandian, Chanro Park, Kangguo Cheng | 2021-09-28 |
| 11127825 | Middle-of-line contacts with varying contact area providing reduced contact resistance | Chanro Park, Kangguo Cheng, Hari Prasad Amanapu | 2021-09-21 |
| 11127623 | Single diffusion cut for gate structures | Hui Zang, Jessica Dechene | 2021-09-21 |