Issued Patents All Time
Showing 301–325 of 1,139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11309319 | Structures and SRAM bit cells integrating complementary field-effect transistors | Randy W. Mann, Bipul C. Paul, Julien Frougier | 2022-04-19 |
| 11309220 | Methods, apparatus, and manufacturing system for self-aligned patterning of a vertical transistor | Chanro Park, Min Gyu Sung | 2022-04-19 |
| 11302794 | FinFET with dual work function metal | Takashi Ando, Alexander Reznicek, Pouya Hashemi | 2022-04-12 |
| 11295988 | Semiconductor FET device with bottom isolation and high-κ first | Julien Frougier, Jingyun Zhang, Alexander Reznicek, Takashi Ando | 2022-04-05 |
| 11295983 | Transistor having source or drain formation assistance regions with improved bottom isolation | Alexander Reznicek, Effendi Leobandung, Jingyun Zhang | 2022-04-05 |
| 11289484 | Forming source and drain regions for sheet transistors | Jingyun Zhang, Xin Miao, Alexander Reznicek | 2022-03-29 |
| 11282961 | Enhanced bottom dielectric isolation in gate-all-around devices | Julien Frougier, Andrew M. Greene, Kangguo Cheng | 2022-03-22 |
| 11282838 | Stacked gate structures | Chen Zhang, Dechao Guo, Junli Wang, Kangguo Cheng, Juntao Li +5 more | 2022-03-22 |
| 11271107 | Reduction of bottom epitaxy parasitics for vertical transport field effect transistors | Tao Li, Tsung-Sheng Kang, Alexander Reznicek | 2022-03-08 |
| 11270935 | Metallization layer formation process | Kangguo Cheng, Chih-Chao Yang, Jing Guo | 2022-03-08 |
| 11264481 | Self-aligned source and drain contacts | Chanro Park, Kangguo Cheng, Juntao Li | 2022-03-01 |
| 11251362 | Stacked spin-orbit-torque magnetoresistive random-access memory | Heng Wu, Julien Frougier, Chen Zhang | 2022-02-15 |
| 11251304 | Wrap-around bottom contact for bottom source/drain | Junli Wang, Alexander Reznicek, Bruce B. Doris | 2022-02-15 |
| 11251301 | Cross-bar vertical transport field effect transistors without corner rounding | Tsung-Sheng Kang, Tao Li, Alexander Reznicek | 2022-02-15 |
| 11251288 | Nanosheet transistor with asymmetric gate stack | Carl Radens, Kangguo Cheng, Juntao Li, Dechao Guo, Tao Li +1 more | 2022-02-15 |
| 11251287 | Self-aligned uniform bottom spacers for VTFETS | Hemanth Jagannathan, Jay William Strane, Eric R. Miller | 2022-02-15 |
| 11244864 | Reducing parasitic capacitance within semiconductor devices | Reinaldo Vega, Alexander Reznicek, Kangguo Cheng | 2022-02-08 |
| 11244861 | Method and structure for forming fully-aligned via | Christopher J. Waskiewicz, Chih-Chao Yang, Huai Huang | 2022-02-08 |
| 11239414 | Physical unclonable function for MRAM structures | Alexander Reznicek, Oscar van der Straten, Koichi Motoyama | 2022-02-01 |
| 11239342 | Vertical transistors having improved control of top source or drain junctions | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2022-02-01 |
| 11239165 | Method of forming an interconnect structure with enhanced corner connection | Christopher J. Waskiewicz, Kangguo Cheng, Chih-Chao Yang | 2022-02-01 |
| 11239119 | Replacement bottom spacer for vertical transport field effect transistors | Heng Wu, Jay William Strane, Hemanth Jagannathan, Lan Yu, Tao Li | 2022-02-01 |
| 11239115 | Partial self-aligned contact for MOL | Veeraraghavan S. Basker, Alexander Reznicek, Junli Wang | 2022-02-01 |
| 11233006 | Metallization lines on integrated circuit products | Lars Liebmann, Daniel Chanemougame, Geng Han | 2022-01-25 |
| 11227923 | Wrap around contact process margin improvement with early contact cut | Veeraraghavan S. Basker, Andrew M. Greene, Alexander Reznicek, Yao Yao | 2022-01-18 |